CAMBRIDGE, United Kingdom — (BUSINESS WIRE) — September 27, 2016 — ARM has released new on-chip interconnect technology delivering the scalability, performance and efficiency demanded across multiple markets including 5G networks, data center infrastructure, HPC, automotive and industrial systems. The ARM® CoreLink® CMN-600 Coherent Mesh Network interconnect and CoreLink DMC-620 Dynamic Memory Controller enable the latest ARM-based SoCs to offer unmatched data throughput and the lowest edge to cloud latency in the market.
“The demands of cloud-based business models require service providers to pack more efficient computational capability into their infrastructure,” said Monika Biddulph, general manager, systems and software group, ARM. “Our new CoreLink system IP for SoCs, based on the ARMv8-A architecture, delivers the flexibility to seamlessly integrate heterogeneous computing and acceleration to achieve the best balance of compute density and workload optimization within fixed power and space constraints.”
The combination of performance and efficiency provided by the third-generation CoreLink coherent backplane products advances the Intelligent Flexible Cloud by enabling efficient compute capability at any point from the edge of the network to the cloud.
Highest-performing coherent backplane IP for intelligent connected
systems
Optimized with the latest ARM Cortex®-A processors,
CoreLink CMN-600 and CoreLink DMC-620 are the industry’s only complete
coherent backplane IP solution for the ARMv8-A architecture. Designers
and system architects can scale high-performance SoC designs from 1 to
128 Cortex-A CPUs (32 clusters) with native ARM AMBA® 5 CHI interfaces,
the industry standard specification for high-performance on-chip
communication. Other key benefits and features include:
- New architecture achieving higher frequencies (2.5 GHz and higher), 50 percent lower latency
- 5x higher throughput and more than 1TB/s of sustained bandwidth
- New Agile System Cache with intelligent cache allocation to enhance any sharing of data between processors, accelerators and interfaces
- Supporting CCIX the open industry standard for coherent multi-chip processor and accelerator connectivity
- CoreLink DMC-620 includes integrated ARM TrustZone® security and supports 1 to 8 channels of DDR4-3200 memory and 3D stacked DRAM for up to 1TB per channel
Accelerated SoC development and system deployment
Advanced
ARM Socrates™ system IP tooling accelerates the bring-up of SoC designs
which integrate ARM coherent backplane IP. ARM intelligence embedded
within CoreLink Creator automates the construction of a scalable custom
mesh interconnect, and can generate RTL in minutes. For automated AMBA
connectivity, ARM Socrates DE is able to rapidly configure and connect
IP blocks.
With ARM Fast Models, software development can begin prior to silicon availability. Fast Models offer a functionally accurate programmer’s view of ARM IP, enabling development of software such as drivers, firmware, OS and applications. Ongoing ARM work with the open source community also accelerates software development time as open source drivers are available for CoreLink IP.
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All information is provided "as is" and without warranty or representation. This document may be shared freely, attributed and unmodified. ARM, AMBA, CoreLink, Cortex, Socrates and TrustZone are trademarks or registered trademarks of ARM Limited (or its subsidiaries). All other brands or product names are the property of their respective holders. © 1995-2016 ARM Group.
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