Evolutionary R-Car Features Improved Computing Performance and Automotive Functionality Safety Support
SANTA CLARA, Calif. — (BUSINESS WIRE) — December 2, 2015 — Renesas Electronics Corporation (TSE: 6723), a premier supplier of advanced semiconductor solutions, today unveiled the third-generation R-Car, an automotive computing platform solution for driving safety support systems and in-vehicle infotainment systems. The new R-Car H3 System-on-Chip (SoC), the first member of the third-generation R-Car, delivers CPU performance, image recognition processing, ISO 26262 (ASIL-B) compliance, and a system in package (SiP) with external memory to enable a wide range of automotive applications.
The R-Car H3 realizes powerful automotive computing performance exceeding that of the predecessor R-Car H2. This enables system manufacturers to utilize the new R-Car H3 as an automotive computing platform to play a key role in the autonomous-driving era.
To make the new device ideal for driving safety support systems, the R-Car H3 provides cognitive computing capabilities, an enhanced computing performance that can process large volumes of information from vehicle sensors accurately in real-time, and enables system manufacturers to run applications that require complex processing, such as obstacle detection, driver status recognition, hazard prediction, and hazard avoidance. To further accelerate the driving safety support systems, the R-Car H3 also conforms to the ISO 26262 (ASIL-B) functionality safety for automotive.
Furthermore, in in-vehicle infotainment systems, the need for connectivity between various systems and services such as smartphones and cloud services is growing. These have led to a significant increase in the volume of data transmitted from outside the system. Therefore, there is a demand for human-machine interface (HMI) computing to process these large amounts of data accurately in real-time. The outstanding performance power of the R-Car H3 makes excellent graphics design possible to realize advanced applications and rich HMI.
The R-Car H3 is an automotive computing platform ideal for the autonomous-driving era with significantly improved cognitive computing and HMI computing capabilities for advanced driving support systems as well as in-vehicle infotainment systems.
Key features of the new R-Car H3:
(1) Support for a wide range of applications as an automotive computing platform
To enable system manufacturers to utilize the R-Car H3 as an automotive computing platform, the new device realizes powerful automotive computing performance exceeding that of the predecessor R-Car H2. To process large amounts of information accurately in real-time, the R-Car H3 is built around the ARM® Cortex®-A57/A53 cores, employing the newest 64-bit CPU core architecture from ARM. It achieves processing performance of 40,000 DMIPS (Dhrystone million instructions per second (Note 1)) for enhanced processing power. The R-Car H3 also features the PowerVR™ GX6650 as the 3-D graphics engine to deliver reliable information to drivers at the right timing. Based on the latest architecture from Imagination Technologies, it delivers approximately three times the shader calculation (Note 2) processing performance of the R-Car H2.
The on-chip IMP-X5 parallel programmable engine offers advanced image recognition technology in addition to the CPU and GPU. Exclusive to Renesas, the IMP-X5 is a recognition engine that is optimized for interoperation with the CPU. It delivers four times the recognition performance of the earlier IMP-X4 image recognition engine, embedded in the second-generation R-Car family.
The R-Car H3 is the first automotive SoC in the world to adopt the 16nm process. By realizing this high performance as well as compliance with the ISO26262 (ASIL-B) standard for automotive functional safety, the R-Car H3 can be used as an automotive computing platform that supports a wide range of applications, including advanced driving safety support systems and in-vehicle infotainment systems.
(2) Improved system level performance based on the results of rich in-vehicle infotainment systems
As the market leader (Note 3) for worldwide in-vehicle infotainment SoC, Renesas has a surpassing system performance based on passed results. Especially by optimizing the internal bus architecture of the SoC, and improving the bandwidth of the DDR memory, the R-Car H3 realizes four times the memory bandwidth compared to the R-Car H2, which enables the system manufacturer to run multiple applications.
Addressing the demand for higher resolution video playback on multiple displays, the R-Car H3 incorporates video codec engine exclusive to Renesas that supports new video compression formats and achieves two times the video playback performance of the R-Car H2.
The R-Car H3 also incorporates enhanced security functions for a more robust boot protection process as well as protection against external cyber-attacks.
The R-Car H3 delivers drastically improved functionality and system level performance, making it possible to utilize the R-Car H3 for a long period of time.
(3) Availability of SiP modules with external memory to reduce the design workload
SiP modules support high-speed external DDR memory interface design with the R-Car H3. As the connection speed between the SoC and DDR memory rises, and the number of signal lines increases, burdens and complexities of PCB design increase. These have become important issues for system manufacturers. By developing modules with an SoC connected to DDR memory, Renesas is reducing the burden as well as the PCB costs and complexities associated with the design. In addition to the SoC and DDR memory, the modules include serial flash memory required for initial boot-up. This means the design tasks from boot-up through DDR memory operation can be eliminated and system manufacturers adopting the R-Car H3 can reduce their design tasks and risks.
The new R-Car H3 maintains a high level of software compatibility with the other SoCs in the R-Car Family already available: the R-Car H2, R-Car M2, and R-Car E2. The R-Car H3 will maintain high level software scalability for the third-generation R-Car Family.
"The R-Car H3 SoC has the all-round sensing, efficiency and safety characteristics that are essential in connected car technologies,” said James McNiven, general manager, CPU group, ARM. “Alongside the inclusion of the high performance ARM® Cortex®-R7 real-time processor, the SoC also capitalizes on the ARM Cortex-A57 and Cortex-A53 cores in an ARM big.LITTLE™ configuration. This has allowed Renesas to deliver advanced vision and detection capabilities while controlling power and achieving the stability that safety-critical electronics demand.”
“Imagination is delighted to see the introduction of the R-Car H3 which includes or our high performance PowerVR GX6650 graphics engine,” said Tony King-Smith, Imagination Technologies EVP marketing. “GX6650 delivers premium graphics performance and features to enable future cockpit experiences, as well as comprehensive GPGPU capabilities.”
“We are pleased to partner with Renesas to provide QNX® software support for the new R-Car H3 SoC,” said John Wall, Senior Vice President and Head of QNX Software Systems, a subsidiary of BlackBerry. “Through this collaboration, we can help accelerate the delivery of next-generation infotainment and ADAS systems that combine the performance of Renesas’ R-Car H3 SoCs with the proven reliability and scalability of QNX OS technology.”
"Next-generation automotive electronics must be designed with security and safety as the top priority,” said Tim Reed, Vice President of Advanced Products, Green Hills Software. “By offering our proven INTEGRITY real-time operating system and Multivisor secure virtualization solutions with the R-Car’s safe and reliable technologies, automotive OEMs and Tier 1’s can be confident in realizing this important design goal.”
Availability
Samples of the R-Car H3 are available now. Mass production is scheduled to begin in March 2018 and is expected to reach a volume of 100,000 units per month in March 2019. (Availability is subject to change without notice.)
(Note 1) DMIPS (Dhrystone million instructions per second): An index of computing performance calculated using the Dhrystone benchmark program.
(Note 2) Shader calculation: A calculation that includes coordinate and color calculation, essential for graphics rendering.
(Note 3) Source: Strategy Analytics Inc., results of 2014, in terms of revenue.
About Renesas Electronics Corporation
Renesas Electronics Corporation (TSE: 6723), the world’s number one supplier of microcontrollers, is a premier supplier of advanced semiconductor solutions including microcontrollers, SoC solutions and a broad-range of analog and power devices. Business operations began as Renesas Electronics in April 2010 through the integration of NEC Electronics Corporation (TSE:6723) and Renesas Technology Corp., with operations spanning research, development, design and manufacturing for a wide range of applications. Headquartered in Japan, Renesas Electronics has subsidiaries in 20 countries worldwide. More information can be found at www.renesas.com.
Separate Sheet
Main Specifications of the R-Car H3 SoC
| Item | R-Car H3 Specifications | |||||||||
| Product No | R-Car H3 (R8J77950 (SiP), R8A77950 (SoC)) | |||||||||
| Power supply voltage |
3.3/1.8 V (IO), 1.1V (LPDDR4), 0.8V (core), 2.5V (EthernetAVB) |
|||||||||
| CPU core |
ARM® CortexTM-A57
|
ARM® CortexTM-A53
|
ARM® CortexTM-R7
|
|||||||
| Cache memory |
L1 Instruction cache:
48 KB L1 Operand cache:
32 KB
|
L1 Instruction cache:
32 KB L1 Operand cache: 32 KB L2 cache: 512 kB |
L1 Instruction cache:
32 KB L1 Operand cache: 32 KB |
|||||||
| External memory |
・LPDDR4-SDRAM
・Maximum operating frequency: 1600 MHz ・Data bus width：32 bits x 4 ch (12.8 GB/s x 4) |
|||||||||
| Expansion bus | PCI Express 2.0 (1 lane) x 2 ch | |||||||||
| Graphics | Imagination Technologies’ PowerVR™ Series 6XT GX6650 | |||||||||
| Video | Display Out x 3 ch | |||||||||
| Video Input x 8 ch | ||||||||||
| Video codec module (H.265, H.264/AV, MPEG-4, VC-1 etc) | ||||||||||
| IP conversion module | ||||||||||
| TS Interface x 2 ch | ||||||||||
| stream and security processor | ||||||||||
| Video image processing (Up and down scaling, Dynamic this press release are trademarks or registered trademarks oresolution processing, Rotation, Visual near lossless image compression) | ||||||||||
| Distortion compensation module x 4 ch (IMR-LSX4) | ||||||||||
| High performance real-time image recognition processor (IMP-X5) | ||||||||||
| Audio | Audio DSP | |||||||||
| Sampling rate converter x 10 ch | ||||||||||
| Serial sound interface x 10 ch | ||||||||||
| MOST DTCP | ||||||||||
| Storage interfaces | USB 3.0 host interface(DRD) x 1 port (wPHY) | |||||||||
| USB 2.0 host/function/OTG interface x 2 port (wPHY) | ||||||||||
| SD host interface x 4 ch (SDR104) | ||||||||||
| Multimedia card interface x 2 ch | ||||||||||
| Serial ATA interface x 1 ch | ||||||||||
|
In car network and
automotive peripherals |
Media local bus (MLB) Interface x１ch (3-pin interface) | |||||||||
| Controller Area Network (CAN-FD support) Interface x 2ch | ||||||||||
|
Ethernet AVB 1.0-compatible MAC built in
Interface: RGMII Ethernet AVB (802.1BA) ・ IEEE802.1BA ・ IEEE802.1AS ・ IEEE802.1Qav ・ IEEE1722 |
||||||||||
| Security | Crypto engine (AES, DES, Hash, RSA) x 2ch | |||||||||
| SystemRAM | ||||||||||
| Other peripherals |
SYS-DMAC x 48 ch, Realtime-DMAC x 16 ch,
Audio-DMAC x 32 ch, Audio(peripheral)-DMAC x 29 ch |
|||||||||
| 32bit timer x 26 ch | ||||||||||
| PWM timer x 7ch | ||||||||||
| I2C bus interface h-DMA | ||||||||||
| Serial communication interface (SCIF) x 11 ch | ||||||||||
| Quad serial peripheral interface (QSPI) x 2 ch (for boot, HyperFlash support) | ||||||||||
|
Clock-synchronized serial interface (MSIOF) x 4 ch（SPI/IIS） |
||||||||||
| Ethernet controller (IEEE802.3u, RGMII, without PHY) | ||||||||||
|
Digital radio interface (DRIF) x 4 ch |
||||||||||
| Interrupt controller (INTC) | ||||||||||
| Clock generator (CPG) with built-in PLL | ||||||||||
| On-chip debugger interface | ||||||||||
| Low power mode | Dynamic Power Shutdown | |||||||||
| AVS (Adaptive Voltage Scaling), DVFS (Dynamic Voltage and Frequency Scaling), DDR-SDRAM power supply backup mode | ||||||||||
| Package |
1255-pin SiP module (42.5 mm x 42.5 mm, 0.8 mm pitch)
138- pin Flip chip BGA (21 mm x 21 mm, 0.5 mm pitch) |
|||||||||
|
Development
environment |
ICE for ARM CPU available from different vendors | |||||||||
| Evaluation board |
A user system development reference platform with the following
features is also available to enable the users to carry out
efficient system development.
(1) Incorporates car information system-oriented peripheral circuits, providing users with an actual device verification environment. (2) Can be used as a software development tool for application software, etc. (3) Allows easy implementation of custom user functions. |
|||||||||
| Software Platform | Support OS: Linux, Android, QNX® Neutrino® RTOS, Integrity® etc | |||||||||
| OpenGL ES3.1 3D graphics library, Wide variety of H.265, H.264, MPEG-4 and VC-1 for video compliant with OpenMAX IL I/F in addition to BSPs compliant with OSs standard API are available to realize complete system concept. | ||||||||||
Remarks: ARM® and Cortex® are registered trademarks of ARM Limited. PowerVR™ is a trademark of Imagination Technologies Limited. Android is a registered trademark from Google Inc. QNX, neutrino and Blackberry are trademarks from BlackBerry Limited, and are used with permission from QNX Software System Limited. Green Hills Software and INTEGRITY are trademarks or registered trademarks of Green Hills Software, Inc. in the U.S. and/or internationally. All names of other products or services mentioned in this press release are trademarks or registered trademarks of their respective owners.
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