Altera Demonstrations Include FPGA-based Heterogeneous Computing Solutions and Real-time Object Detection and Recognition Using Neural Network Algorithms

San Jose, Calif – Altera Corporation (Nasdaq: ALTR) today announced it will showcase at the Intel Developers Forum (IDF) how FPGA accelerators are being used to enable networking, security and machine learning workloads in a power and cost efficient way. Altera’s participation at IDF15 includes in-booth demonstrations (booth #359) and technical presentations. IDF15 takes place in San Francisco, Calif., August 18-20, 2015 at the Moscone Center West.

FPGAs provide a platform to significantly increase compute performance and data processing while reducing system costs and power in high-performance computing and data center applications. The technologies Altera is highlighting at IDF15 showcase the use of FPGAs to provide high-bandwidth, low-latency connections to network and storage systems, as well as using FPGAs for compression, data filtering, and algorithmic acceleration.
 
In-booth Demonstrations Include:

• Heterogeneous Computing System Using QPI: This demonstration connects an Intel® Xeon® processor to a high-performance Arria® 10 FPGA using the QPI protocol. The FPGA is configured as the home agent and shows how FPGAs can be used as a power efficient co-processor for the CPU.

• Real-time Object Detection and Recognition: This demonstration shows the utility of FPGAs to efficiently run complex neural network algorithms for use in deep learning systems.

Altera will also deliver a neural networks presentation to IDF15 attendees that describe the use of FPGAs to accelerate neural network algorithms in machine learning systems. Neural networks are used today to solve complex computation problems by modeling and approximating results based on a large number of data inputs. The flexibility and efficiency of an FPGA make them an ideal solution to run neural network algorithms. This session is being held on August 18 at 6:30 p.m. in the Networking Plaza at IDF15 and will describe to attendees how to develop complex convolutional neural networks in software for implementation in FPGA offload engines using OpenCL.