DCD’s DI2CSB IP Core is a two wire, bidirectional serial bus, which provides stable and efficient short distance data transmission between numerous devices. A very simple interface, composed with read, write and data signals, allows easy connection to target device. The DI2CSB is a technology independent design, that’s why it can be implemented in a variety of both ASIC and FPGA technologies.

Bytom, Poland. 5^th of May 2014 ---- Digital Core Design, celebrating its 15^th anniversary in 2014, enhanced its portfolio with a new architecture. The DI2CSB provides an interface between a passive target device e.g. memory, LCD display, pressure sensors etc., and an I2C bus. - It can work as a slave receiver or as a transmitter – says Piotr Kandora, DCD’s Member of the Board - depending on the working mode determined by the master device. A clever interface, composed with read, write and data signals, allows easy connection to target devices. The core does not require any programming and is ready to work after power up/reset. The read, write, burst read, burst write and repeated start transmissions are automatically recognized by the core. – The DI2CSB core incorporates all features required by the I2C specification – adds Kandora – that’s why it supports Standard, Fast, Fast Plusand High Speedtransmission modes.

The DI2CSB can be easily customized in accordance to project’s needs. For instance, the DI2CSB can be found in embedded microprocessor boards, consumer and professional audio/video, home and automotive radio, low-power applications, communication systems, cost-effective reliable automotive systems etc.

More information: http://dcd.pl/ipcore/121/di2csb/

DI2CSB Features:

• Conforms to the latest I2C specification
• Slave operation
• Slave transmitter
• Slave receiver
• Supports 3 transmission speed modes
• Standard (up to 100 kb/s)
• Fast (up to 400 kb/s)
• Fast Plus (up to 1 Mb/s)
• High Speed (up to 3,4 Mb/s)
• Allows operation from a wide range of input clock frequencies
• Support for reads, writes, burst reads, burst writes, and repeated start
• 7-bit addressing
• No programming required

Simple interface allows easy connection to target device e.g. memory, LCD display, pressure sensors etc.

• Fully synthesizable
• Static synchronous design
• Positive edge clocking and no internal tri-states
• Scan test ready

Information about Digital Core Design:

In 2014 Digital Core Design celebrates its 15^th Anniversary. The company founded in 1999, since the beginning stands in the forefront of the IP Core market. High specialization and profound customer service enabled to introduce more than 70 different architectures. Among them is the world’s fastest 8051 IP Core, the DQ80251, which is more than 66 times faster than the standard solution. As an effect, over 300 hundred licensees have been sold to more than 500 companies worldwide. Among them are the biggest enterprises like e.g. Sony, Siemens, General Electric and Toyota. But a lot of DCD’s customers are small businesses, R&D laboratories or front/back end offices, which require exact solution tailored to their project needs. Rough estimations say that more than 250 000 000 devices around the globe have been based on Digital Core Design’s IP Cores.


Contact:

Tomeq Cwienk
Digital Core Design
ul. Wroclawska
Bytom, Poland
tel: + 48 32 282 82 66 ext.25
mail to: Email Contact