Avery Design Systems Announces UFS Host Controller UFSHCI Verification Solution
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Avery Design Systems Announces UFS Host Controller UFSHCI Verification Solution

ANDOVER, Mass. — (BUSINESS WIRE) — October 8, 2013 — Avery Design Systems Inc., a leader in verification IP, today announced availability of its UFS Host Controller Interface (JESD223 UFSHCI) verification solution supporting the latest embedded mobile storage solutions comprised of MIPI UniPro and M-PHY, and JEDEC UFS specifications.

The new release of MIPI-Xactor allows design and verification engineers to quickly and extensively test the functionality of both UFSHCI-compliant host controllers and UFS devices.

Avery provides a complete verification solution consisting of SystemVerilog UVM/OVM/VMM compliant models and environment, protocol checkers, directed and random compliance test suites, and reference verification frameworks. Additional advanced debug features include multi-level analyzer trackers to visualize data and control flow through the protocol stacks.

Key Features

Key BFM Features

About Avery Design Systems

Founded in 1999, Avery Design Systems, Inc. enables system and SOC design teams to achieve dramatic functional verification productivity improvements through the use of formal analysis applications for automatic property and coverage generation and RT-level and gate-level X verification; robust core-through-chip-level Verification IP for PCI Express, USB, AMBA, UFS, MIPI, DDR/LPDDR, NVM Express, SCSI Express, SATA Express, eMMC, and SD/SDIO standards. The company is a member of the Mentor Graphics Value Added Partnership (VAP) program and has established numerous Avery Design VIP partner program affiliations with leading IP suppliers. More information about the company may be found at www.avery-design.com.



Contact:

Avery Design Systems
Chris Browy, 978-689-7286
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