SuperTest – helping bring AI edge computing to next-generation Intelligent Connected Vehicles

North American PCB Industry Sales Down 6.8 Percent in May

NY CREATES and CEA-Leti Announce Strategic Research Partnership

True Circuits Introduces the JSPICE™ Design Environment (JDE™) at the Design Automation Conference Will also Showcase High-performance PLL, DLL and DDR PHY IP

Interview with Magdy Abadir, CEO, Suitera

Silicon Catalyst Ventures launched to support Early-stage Semiconductor Startups

Calista Redmond, CEO RISC-V

NVIDIA CEO Jensen Huang Keynote at CES 2025 Nvidia

SuperGuard Library Safety Qualification Suite - Solid Sands Solid Sands

EDACafe Editorial by Sanjay Gangal Cadence’s Shift-Left Approach and the Future of Advanced Package Design

Bridging the Frontier by Bob Smith, Executive Director ESD Alliance Members Exhibit at Next Week’s DVCon in San Jose

Industry Predictions by Sanjay Gangal Hyperlabs Expands Its High-Frequency Horizons at DesignCon 2025

EDACafe Editorial by Sanjay Gangal A New Era in Semiconductor Manufacturing: Pragmatic Semiconductor’s Vision for a Flexible Future

EDACafe Editorial by Sanjay Gangal Arm Reports Record Revenue as AI, Cloud Demand Accelerate Growth

Senior Platform Software Engineer, AI Server - GPU for Nvidia at Santa Clara, California

Senior Firmware Architect - Server Manageability for Nvidia at Santa Clara, California

Sr. Silicon Design Engineer for AMD at Santa Clara, California

CAD Engineer for Nvidia at Santa Clara, California

GPU Design Verification Engineer for AMD at Santa Clara, California

DVCon U.S. 2025 at United States - Feb 24 - 27, 2025

Design, Automation & Test in Europe - DATE 2025 at Palais des congrès de Lyon Lyon France - Mar 31 - 2, 2025

DATE 2025 - Design, Automation and Test in Europe Conference at France - Mar 31 - 2, 2025

SEMIEXPO Heartland 2025 at Indiana Convention Center 100 S. Capitol Ave. Indianapolis IN - Apr 1 - 2, 2025