CebaTech Changes Company Name to Altior

CebaTech Appoints Adam T. Drobot, Ph.D. as Chairman of the Board

SuperGuard Library Safety Qualification Suite - Solid Sands Solid Sands

Calista Redmond, CEO RISC-V

Lou Ternullo, Senior Director of IP Product Management Rambus

EDACafe Editorial by Roberto Frazzoli Shifting left software development; advancements in car power architectures; Japan’s semiconductor subsidies; ADI acquires Flex Logix

Industry Predictions by Sanjay Gangal Intel’s New Xeon 6 SoC Redefines vRAN Efficiency, Single-Server Footprint for Cell Sites

EDACafe Editorial by Sanjay Gangal Siemens’ Innexis Suite Advances Shift Left for Faster, Earlier IC Development

Siemens EDA by Romain Petit Multi-FPGA Partitioning – What’s the Recipe for Success?

Guest Blogger by Sanjay Gangal NVIDIA’s RISC-V Transformation: How Open Architecture Became Central to AI and Computing

CAD Engineer for Nvidia at Santa Clara, California

Design Verification Engineer for Blockwork IT at Milpitas, California

Sr. Silicon Design Engineer for AMD at Santa Clara, California

GPU Design Verification Engineer for AMD at Santa Clara, California

Senior Firmware Architect - Server Manageability for Nvidia at Santa Clara, California

Senior Platform Software Engineer, AI Server - GPU for Nvidia at Santa Clara, California

SEMICON Japan 2024 at Tokyo Big Sight Tokyo Japan - Dec 11 - 13, 2024

PDF Solutions AI Executive Conference at St. Regis Hotel San Francisco - Dec 12, 2024

DVCon U.S. 2025 at United States - Feb 24 - 27, 2025

DATE 2025 - Design, Automation and Test in Europe Conference at France - Mar 31 - 2, 2025