Synopsys and SiMa.ai Announce Strategic Collaboration to Accelerate Development of Automotive Edge AI Solutions

Rapidus Collaborates with Synopsys to Shorten Semiconductor Design Cycles

Silvaco Joins SMART USA Institute to Propel Digital Twin Innovations Under CHIPS Manufacturing USA Program

Marvell Technology, Inc. Reports Third Quarter of Fiscal Year 2025 Financial Results

AST SpaceMobile and Cadence Collaborate to Advance the World’s First and Only Planned Space-Based Global Cellular Broadband Network

Marvell Expands Strategic Collaboration with AWS to Enable Accelerated Infrastructure for AI in the Cloud

JB Baker, VP Products ScaleFlux

Arm, Exostellar Boost AI Cloud for Chip Design Exostellar

Firas Mohamed President IROC Technologies

EDACafe Editorial by Roberto Frazzoli NeurIPS; advanced packaging; OCTRAM memory; graphene interconnect; Google’s quantum advancements

Guest Blogger by Sanjay Gangal Intel Foundry Unveils Breakthroughs in Transistor and Packaging Technologies at IEDM 2024

The Dominion of Design by Sanjay Gangal EDACafe Industry Predictions for 2025 – Semidynamics

Siemens EDA by Sanjay Gangal Siemens’ Next-Gen Electronic Systems Design Platform: A Unified Vision of AI, Collaboration, and Innovation

Bridging the Frontier by Paul Cohen ESD Alliance Kicks off “Savage on Security” Webinar Series January 23 with Warren Savage

GPU Design Verification Engineer for AMD at Santa Clara, California

Sr. Silicon Design Engineer for AMD at Santa Clara, California

ESD Alliance "Savage on Security” Webinar at United States - Jan 23, 2025

SEMICON Korea 2025 at Hall A, B, C, D, E, GrandBallroom, PLATZ, COEX, Seoul Korea (South) - Feb 19 - 21, 2025

DVCon U.S. 2025 at United States - Feb 24 - 27, 2025

Design, Automation & Test in Europe - DATE 2025 at Palais des congrès de Lyon Lyon France - Mar 31 - 2, 2025