Faraday Unveils HiSpeedKit™-HS Platform for High-speed Interface IP Verification in SoCs

SiFive HiFive Premier P550 Development Boards Now Shipping

Andes Announces the AndesCore™ 46-Series Family and the 3rd generation Vector Processor AX46MPV with Matrix Extension

Microchip’s RTG4™ FPGAs with Lead-Free Flip-Chip Bumps Achieve Highest Space Qualification

ACL Digital Joins the Intel Foundry Accelerator Design Services Alliance

indie Semiconductor’s Latest Vision Processor Design-win Momentum Accelerates, Awarded Sensor Innovation of the Year

Calista Redmond, CEO RISC-V

Arm, Exostellar Boost AI Cloud for Chip Design Exostellar

JB Baker, VP Products ScaleFlux

EDACafe Editorial by Roberto Frazzoli NeurIPS; advanced packaging; OCTRAM memory; graphene interconnect; Google’s quantum advancements

Guest Blogger by Sanjay Gangal Intel Foundry Unveils Breakthroughs in Transistor and Packaging Technologies at IEDM 2024

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Bridging the Frontier by Paul Cohen ESD Alliance Kicks off “Savage on Security” Webinar Series January 23 with Warren Savage

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ESD Alliance "Savage on Security” Webinar at United States - Jan 23, 2025

DVCon U.S. 2025 at United States - Feb 24 - 27, 2025

Design, Automation & Test in Europe - DATE 2025 at Palais des congrès de Lyon Lyon France - Mar 31 - 2, 2025

DATE 2025 - Design, Automation and Test in Europe Conference at France - Mar 31 - 2, 2025