Andes Technology Unveils the D45-SE RISC-V Processor Targeting ASIL-D Certification

SensiML Expands Platform Support to Include the RISC-V Architecture

LDRA Announces Extended Support for RISC-V High Assurance Software Quality Tool Suite to Accelerate On-Target Testing of Critical Embedded Applications

OpenHW Group to Join the Eclipse Foundation, Expanding Open Source RISC-V Innovation

SiFive Highlights Key Inflection Points Driving RISC-V Adoption for AI and Introduces Intelligence XM Series for AI Workload Acceleration

SEALSQ Adopts RISC-V the Open-Standard RISC-V Architecture; Achievement Aligns with Rising Global Demand for Edge-AI and Machine Learning Applications

SuperGuard Library Safety Qualification Suite - Solid Sands Solid Sands

Anthony Dawson, VP ANSYS

John Eble, VP Rambus

EDACafe Editorial by Roberto Frazzoli Nvidia-powered CAE acceleration; new Keysight EDA software; CoWoS roadmap; new datacenter inference solution

Bridging the Frontier by Paul Cohen Honoring Dr. Jason Cong During the Phil Kaufman Award Ceremony and Banquet

Industry Predictions by Sanjay Gangal Intel’s New Xeon 6 SoC Redefines vRAN Efficiency, Single-Server Footprint for Cell Sites

EDACafe Editorial by Sanjay Gangal Siemens’ Innexis Suite Advances Shift Left for Faster, Earlier IC Development

Siemens EDA by Romain Petit Multi-FPGA Partitioning – What’s the Recipe for Success?

CAD Engineer for Nvidia at Santa Clara, California

Sr. Silicon Design Engineer for AMD at Santa Clara, California

Design Verification Engineer for Blockwork IT at Milpitas, California

Senior Platform Software Engineer, AI Server - GPU for Nvidia at Santa Clara, California

GPU Design Verification Engineer for AMD at Santa Clara, California

Senior Firmware Architect - Server Manageability for Nvidia at Santa Clara, California

SEMICON Japan 2024 at Tokyo Big Sight Tokyo Japan - Dec 11 - 13, 2024

PDF Solutions AI Executive Conference at St. Regis Hotel San Francisco - Dec 12, 2024

DVCon U.S. 2025 at United States - Feb 24 - 27, 2025

DATE 2025 - Design, Automation and Test in Europe Conference at France - Mar 31 - 2, 2025