Cadence Digital Full Flow Achieves Certification for GlobalFoundries® 12LP/12LP+ Process Platforms

Scala Computing and Zebra Technologies Deploy Collaboration Design Environment Using Cadence Tools on the Cloud

Joe Costello, ex-CEO of Cadence joined Anari AI: “There must be a new approach to the design of chips for high-performance computing applications”

SiTime Precision Timing Technology Enables Cadence’s Emulation and Prototyping Platforms with Quick and Easy Adoption

Cadence Reports First Quarter 2022 Financial Results

Cadence Ushers in New Era of Performance and Accuracy for Multiphysics System Simulation with Fidelity CFD

Josep Montanya , CEO Nanusens

Ricky Lau, CTO The Six Semiconductor

Arm, Exostellar Boost AI Cloud for Chip Design Exostellar

EDACafe Editorial by Roberto Frazzoli Nvidia-powered CAE acceleration; new Keysight EDA software; CoWoS roadmap; new datacenter inference solution

Siemens EDA by Sanjay Gangal Enhance power reliability through design-stage layout optimization

Bridging the Frontier by Paul Cohen Honoring Dr. Jason Cong During the Phil Kaufman Award Ceremony and Banquet

Industry Predictions by Sanjay Gangal Intel’s New Xeon 6 SoC Redefines vRAN Efficiency, Single-Server Footprint for Cell Sites

EDACafe Editorial by Sanjay Gangal Siemens’ Innexis Suite Advances Shift Left for Faster, Earlier IC Development

Sr. Silicon Design Engineer for AMD at Santa Clara, California

Senior Platform Software Engineer, AI Server - GPU for Nvidia at Santa Clara, California

CAD Engineer for Nvidia at Santa Clara, California

GPU Design Verification Engineer for AMD at Santa Clara, California

Design Verification Engineer for Blockwork IT at Milpitas, California

SEMICON Japan 2024 at Tokyo Big Sight Tokyo Japan - Dec 11 - 13, 2024

PDF Solutions AI Executive Conference at St. Regis Hotel San Francisco - Dec 12, 2024

DVCon U.S. 2025 at United States - Feb 24 - 27, 2025

DATE 2025 - Design, Automation and Test in Europe Conference at France - Mar 31 - 2, 2025