Axis launches 8th generation ARTPEC system-on-chip powering deep-learning analytics on the edge

Avalanche Technology partners with LinearASICs on Chiplets for its Space Grade MRAM products

ADLINK launches COM-HPC server modules with 80-core Ampere® Altra® Arm-based SoCs for embedded applications

Silicon Labs Unveils World's First Secure Sub-GHz SoCs With 1+ Mile Wireless Range And 10+ Year Battery Life

NeuReality collaborates with Xilinx to deliver NeuReality's novel AI-centric server to the market

SmartDV Provides Broad Portfolio of Memory Modeling, Design and Verification Solutions

Josep Montanya , CEO Nanusens

Ricky Lau, CTO The Six Semiconductor

Arm, Exostellar Boost AI Cloud for Chip Design Exostellar

EDACafe Editorial by Roberto Frazzoli Nvidia-powered CAE acceleration; new Keysight EDA software; CoWoS roadmap; new datacenter inference solution

Siemens EDA by Sanjay Gangal Enhance power reliability through design-stage layout optimization

Bridging the Frontier by Paul Cohen Honoring Dr. Jason Cong During the Phil Kaufman Award Ceremony and Banquet

Industry Predictions by Sanjay Gangal Intel’s New Xeon 6 SoC Redefines vRAN Efficiency, Single-Server Footprint for Cell Sites

EDACafe Editorial by Sanjay Gangal Siemens’ Innexis Suite Advances Shift Left for Faster, Earlier IC Development

Senior Platform Software Engineer, AI Server - GPU for Nvidia at Santa Clara, California

Design Verification Engineer for Blockwork IT at Milpitas, California

GPU Design Verification Engineer for AMD at Santa Clara, California

CAD Engineer for Nvidia at Santa Clara, California

Sr. Silicon Design Engineer for AMD at Santa Clara, California

SEMICON Japan 2024 at Tokyo Big Sight Tokyo Japan - Dec 11 - 13, 2024

PDF Solutions AI Executive Conference at St. Regis Hotel San Francisco - Dec 12, 2024

DVCon U.S. 2025 at United States - Feb 24 - 27, 2025

DATE 2025 - Design, Automation and Test in Europe Conference at France - Mar 31 - 2, 2025