AndesBoardFarm Enables SoC Designers to Explore RISC-V Processors in Online FPGA Board Collection

Lattice Propel Design Environment Supports New RISC-V Processor and IP Cores

Bluespec, Inc. Joins the Xilinx® Partner Program, Offering Drop-in Ready RISC-V Processors for Xilinx FPGAs

Andes Announces the New Upgrade of AndeSight™ IDE v5.0: a comprehensive software solution to accelerate RISC-V AI and IoT developments

Renesas and SiFive Partner to Jointly-Develop Next-Generation High-End RISC-V Solutions for Automotive Applications

SiFive and DARPA Collaborate to Bring the Power of RISC-V to Technology Innovation

Josep Montanya , CEO Nanusens

SuperGuard Library Safety Qualification Suite - Solid Sands Solid Sands

Arm, Exostellar Boost AI Cloud for Chip Design Exostellar

EDACafe Editorial by Roberto Frazzoli Nvidia-powered CAE acceleration; new Keysight EDA software; CoWoS roadmap; new datacenter inference solution

Siemens EDA by Sanjay Gangal Enhance power reliability through design-stage layout optimization

Bridging the Frontier by Paul Cohen Honoring Dr. Jason Cong During the Phil Kaufman Award Ceremony and Banquet

Industry Predictions by Sanjay Gangal Intel’s New Xeon 6 SoC Redefines vRAN Efficiency, Single-Server Footprint for Cell Sites

EDACafe Editorial by Sanjay Gangal Siemens’ Innexis Suite Advances Shift Left for Faster, Earlier IC Development

Senior Platform Software Engineer, AI Server - GPU for Nvidia at Santa Clara, California

Senior Firmware Architect - Server Manageability for Nvidia at Santa Clara, California

CAD Engineer for Nvidia at Santa Clara, California

GPU Design Verification Engineer for AMD at Santa Clara, California

Sr. Silicon Design Engineer for AMD at Santa Clara, California

Design Verification Engineer for Blockwork IT at Milpitas, California

SEMICON Japan 2024 at Tokyo Big Sight Tokyo Japan - Dec 11 - 13, 2024

PDF Solutions AI Executive Conference at St. Regis Hotel San Francisco - Dec 12, 2024

DVCon U.S. 2025 at United States - Feb 24 - 27, 2025

DATE 2025 - Design, Automation and Test in Europe Conference at France - Mar 31 - 2, 2025