Green Hills Software Adds RTOS Support to Its Extensive Product Portfolio for RISC-V-based SoCs

Seagate Designs RISC-V Cores to Power Data Mobility and Trustworthiness

Valtrix Broadens Support For RISC-V Design Verification With Latest Updates To STING

OneSpin Contributes to the OpenHW Ecosystem to Achieve Processor Integrity for the CORE-V CVE4 Open-Source RISC-V Cores

QuickLogic On Keynote Panel at RISC-V Summit

Andes RISC-V Vector Processor NX27V Is Upgraded to RVV 1.0

Lou Ternullo, Senior Director of IP Product Management Rambus

SuperGuard Library Safety Qualification Suite - Solid Sands Solid Sands

Josep Montanya , CEO Nanusens

EDACafe Editorial by Roberto Frazzoli Nvidia-powered CAE acceleration; new Keysight EDA software; CoWoS roadmap; new datacenter inference solution

Siemens EDA by Sanjay Gangal Enhance power reliability through design-stage layout optimization

Bridging the Frontier by Paul Cohen Honoring Dr. Jason Cong During the Phil Kaufman Award Ceremony and Banquet

Industry Predictions by Sanjay Gangal Intel’s New Xeon 6 SoC Redefines vRAN Efficiency, Single-Server Footprint for Cell Sites

EDACafe Editorial by Sanjay Gangal Siemens’ Innexis Suite Advances Shift Left for Faster, Earlier IC Development

Sr. Silicon Design Engineer for AMD at Santa Clara, California

GPU Design Verification Engineer for AMD at Santa Clara, California

Design Verification Engineer for Blockwork IT at Milpitas, California

CAD Engineer for Nvidia at Santa Clara, California

Senior Platform Software Engineer, AI Server - GPU for Nvidia at Santa Clara, California

Senior Firmware Architect - Server Manageability for Nvidia at Santa Clara, California

SEMICON Japan 2024 at Tokyo Big Sight Tokyo Japan - Dec 11 - 13, 2024

PDF Solutions AI Executive Conference at St. Regis Hotel San Francisco - Dec 12, 2024

DVCon U.S. 2025 at United States - Feb 24 - 27, 2025

DATE 2025 - Design, Automation and Test in Europe Conference at France - Mar 31 - 2, 2025