Achronix Demonstrates Silicon Validation Device with 112 Gbps SerDes

Synopsys Announces Collaboration with Samsung Foundry to Offer Secure and Scalable Environment on the Cloud for IC Design and Verification

Synopsys Fusion Design Platform Extends Leadership at 7nm, Surpasses 100 Tapeout Milestone in First Year

MEDIA ALERT: ESD Alliance Hosts Fireside Chat with Jim Hogan and Cadence’s Paul Cunningham

EMA Launches Ultra Librarian Model Cloud on Maxim Integrated's Website

Synopsys Unveils IC Validator NXT to Cut Physical Signoff Cycle by 2X

Magdy Abadir, CEO Suitera

Arm, Exostellar Boost AI Cloud for Chip Design Exostellar

Ricky Lau, CTO The Six Semiconductor

EDACafe Editorial by Roberto Frazzoli Rapidus advancements; automotive AI updates; CHIPS Act supporting SOI and SiC fabs; Qualcomm-Arm legal battle

Industry Predictions by Sanjay Gangal EDACafe Industry Predictions for 2025 – Point2 Technology

Siemens EDA by Juergen Jaeger FPGA-based prototyping – to build, or to buy, that is the question!

Guest Blogger by Sanjay Gangal Intel Foundry Unveils Breakthroughs in Transistor and Packaging Technologies at IEDM 2024

The Dominion of Design by Sanjay Gangal EDACafe Industry Predictions for 2025 – Semidynamics

Consumer Electronics Show 2025 - CES 2025 at Las Vegas Convention Center NV - Jan 7 - 10, 2025

ESD Alliance "Savage on Security” Webinar at United States - Jan 23, 2025

SEMICON Korea 2025 at Hall A, B, C, D, E, GrandBallroom, PLATZ, COEX, Seoul Korea (South) - Feb 19 - 21, 2025

DVCon U.S. 2025 at United States - Feb 24 - 27, 2025