Mentor extends support of tools and solutions for Samsung Foundry's 8LPP and 7LPP process technologies

Mentor launches Calibre RealTime Digital to help cut weeks off of IC design signoff

Mentor Veloce hardware emulation platform now available on Amazon Web Services

Mentor extends Capital for efficient design of SAE J1939-based CAN networks

Samsung's 8LPP process reference flow leverages Mentor Tessent tools for large design test-time savings

Mentor expands the Veloce emulation platform with Veloce StratoT

Andrew Baker , CEO Orca Semi

Calista Redmond, CEO RISC-V

Lou Ternullo, Senior Director of IP Product Management Rambus

EDACafe Editorial by Roberto Frazzoli Nvidia-powered CAE acceleration; new Keysight EDA software; CoWoS roadmap; new datacenter inference solution

Siemens EDA by Sanjay Gangal Enhance power reliability through design-stage layout optimization

Bridging the Frontier by Paul Cohen Honoring Dr. Jason Cong During the Phil Kaufman Award Ceremony and Banquet

Industry Predictions by Sanjay Gangal Intel’s New Xeon 6 SoC Redefines vRAN Efficiency, Single-Server Footprint for Cell Sites

EDACafe Editorial by Sanjay Gangal Siemens’ Innexis Suite Advances Shift Left for Faster, Earlier IC Development

CAD Engineer for Nvidia at Santa Clara, California

Sr. Silicon Design Engineer for AMD at Santa Clara, California

GPU Design Verification Engineer for AMD at Santa Clara, California

Design Verification Engineer for Blockwork IT at Milpitas, California

Senior Firmware Architect - Server Manageability for Nvidia at Santa Clara, California

Senior Platform Software Engineer, AI Server - GPU for Nvidia at Santa Clara, California

SEMICON Japan 2024 at Tokyo Big Sight Tokyo Japan - Dec 11 - 13, 2024

PDF Solutions AI Executive Conference at St. Regis Hotel San Francisco - Dec 12, 2024

DVCon U.S. 2025 at United States - Feb 24 - 27, 2025

DATE 2025 - Design, Automation and Test in Europe Conference at France - Mar 31 - 2, 2025