Xilinx Launches Vivado Design Suite HLx Editions, Bringing Ultra High Productivity to Mainstream System & Platform Designers

Keysight Technologies, UCSD, Demonstrate World’s First 5G, 100 to 200 Meter Communication Link up to 2 Gbps

Hisense Launches China's First Independently-developed Graphics Engine Chip

Altera Functional Safety Package Combines FPGA Flexibility with "Lockstep" Processor Solution to Reduce Risk and Time-to-Market

Macronix High Performance Quad SPI NOR Flash Products Power Xilinx UltraScale(TM) FPGAs for the Aerospace & Defense Market

TI introduces industry's first industrial drive control system-on-chip (SoC) to support digital and analog position sensors

JB Baker, VP Products ScaleFlux

Firas Mohamed President IROC Technologies

Ricky Lau, CTO The Six Semiconductor

EDACafe Editorial by Roberto Frazzoli Nvidia-powered CAE acceleration; new Keysight EDA software; CoWoS roadmap; new datacenter inference solution

Siemens EDA by Sanjay Gangal Enhance power reliability through design-stage layout optimization

Bridging the Frontier by Paul Cohen Honoring Dr. Jason Cong During the Phil Kaufman Award Ceremony and Banquet

Industry Predictions by Sanjay Gangal Intel’s New Xeon 6 SoC Redefines vRAN Efficiency, Single-Server Footprint for Cell Sites

EDACafe Editorial by Sanjay Gangal Siemens’ Innexis Suite Advances Shift Left for Faster, Earlier IC Development

CAD Engineer for Nvidia at Santa Clara, California

Senior Firmware Architect - Server Manageability for Nvidia at Santa Clara, California

Senior Platform Software Engineer, AI Server - GPU for Nvidia at Santa Clara, California

Sr. Silicon Design Engineer for AMD at Santa Clara, California

GPU Design Verification Engineer for AMD at Santa Clara, California

Design Verification Engineer for Blockwork IT at Milpitas, California

SEMICON Japan 2024 at Tokyo Big Sight Tokyo Japan - Dec 11 - 13, 2024

PDF Solutions AI Executive Conference at St. Regis Hotel San Francisco - Dec 12, 2024

DVCon U.S. 2025 at United States - Feb 24 - 27, 2025

DATE 2025 - Design, Automation and Test in Europe Conference at France - Mar 31 - 2, 2025