IDT and Altera Simplify SyncE Compliance for Ethernet Node Designs

Intel Chooses Averna for Testing DOCSIS 3.1 Chipsets

Avnet Introduces New “ARTY” Xilinx Artix-7 35T FPGA Evaluation Kit

Microsemi's New Libero SoC v11.6 Software Enhances Ease of Use for its Award-Winning SmartFusion2 SoC FPGAs and IGLOO2 FPGAs

ViaSat to License Its Digital Signal Processing and Forward Error Correction IP Cores for Next-Generation 100G Optical Transport

MoSys to Showcase 100G LineSpeed PHY and Bandwidth Engine Intelligent Memory Products for High Density 100G to Terabit Networking Equipment at ECOC 2015

Magdy Abadir, CEO Suitera

Josep Montanya , CEO Nanusens

Firas Mohamed President IROC Technologies

EDACafe Editorial by Roberto Frazzoli Nvidia-powered CAE acceleration; new Keysight EDA software; CoWoS roadmap; new datacenter inference solution

Siemens EDA by Sanjay Gangal Enhance power reliability through design-stage layout optimization

Bridging the Frontier by Paul Cohen Honoring Dr. Jason Cong During the Phil Kaufman Award Ceremony and Banquet

Industry Predictions by Sanjay Gangal Intel’s New Xeon 6 SoC Redefines vRAN Efficiency, Single-Server Footprint for Cell Sites

EDACafe Editorial by Sanjay Gangal Siemens’ Innexis Suite Advances Shift Left for Faster, Earlier IC Development

GPU Design Verification Engineer for AMD at Santa Clara, California

Design Verification Engineer for Blockwork IT at Milpitas, California

Senior Firmware Architect - Server Manageability for Nvidia at Santa Clara, California

CAD Engineer for Nvidia at Santa Clara, California

Sr. Silicon Design Engineer for AMD at Santa Clara, California

Senior Platform Software Engineer, AI Server - GPU for Nvidia at Santa Clara, California

SEMICON Japan 2024 at Tokyo Big Sight Tokyo Japan - Dec 11 - 13, 2024

PDF Solutions AI Executive Conference at St. Regis Hotel San Francisco - Dec 12, 2024

DVCon U.S. 2025 at United States - Feb 24 - 27, 2025

DATE 2025 - Design, Automation and Test in Europe Conference at France - Mar 31 - 2, 2025