"Mentor's Reference Flow 11.0 track has expanded to cover the entire IC design and verification cycle, from electronic system level design through functional verification, implementation and test," said S.T. Juang, senior director of Design Infrastructure Marketing at TSMC. "As TSMC customers move to 28nm and beyond, they want tools that allow them to work at higher levels of abstraction, and give them confidence that their designs can meet performance and low power goals and achieve yields that TSMC processes are capable of delivering. The Mentor Reference Flow 11.0 track meets those requirements."
Electronic System Level Design, High-level Synthesis and Functional Verification
The Vista
electronic system level (ESL) design and verification platform supports optimizing performance and power at the architectural level on a TLM2.0 transaction-level platform. The Vista platform also enables validation and debug at the TLM level and supports virtual prototyping for early software validation and debug.
For the TSMC ESL verification reference flow, the Vista platform facilities reuse of C++ models and stimulus functions in the Vista TLM2.0 models, and the validation and debug at the TLM level of the assembled transaction level platforms. In addition, the Mentor ESL flow allows reuse of the Vista platform created TLMs in Open Verification Methodology (OVM) block level configurations running on the Questa® functional verification platform and the reuse of C++ models in the Catapult C SCVerify flow.
The Catapult C synthesis tool synthesizes ANSI C++ code to production quality RTL, significantly reducing the time to verified RTL without sacrificing quality of results (QoR). In the HLS RF11 flow, a production quality design and verification flow is established showing C code to gates targeting TSMC 65nm and 40nm low-power process technologies. A key new feature shown is integration with the TSMC Memory Compiler to provide on-the-fly memory generation for verification and RTL synthesis. The flow includes Catapult C libraries for TSMC standard cell and memory libraries, which are central to the Catapult C technology-aware, high-level synthesis engine. In addition, Reference Flow 11.0 illustrates Catapult C's ability to explore various power, performance and area implementations, which allows designers to manage algorithms, control-logic and low-power implementations to achieve full-chip applicability.
Mentor's Questa functional verification platform is a comprehensive ESL to RTL to gate-level verification solution. The Questa platform promotes efficient ESL verification reuse supporting stimulus and reference model reuse from ESL through RTL to gate-level descriptions based on the OVM. Users write their testbench and reference models once. As the design is refined from high-levels of abstraction to gate-level implementation, the built-in multi-lingual features of the Questa platform give users smooth and seamless transition for significantly reduced errors associated with hand recoding and increased productivity.
For low-power design, Mentor's 0-In® Formal tool with Clock-Domain Crossing and AutoCheck features are included for formal verification.
IC Implementation, Physical Verification and Testing
New capabilities in the Olympus-SoC place-and-route system make it ready for TSMC's most advanced processes including complete support for TSMC 28nm routing rules, stage-based on-chip variation (OCV) tables for clock and data paths, and context- dependent timing, power and placement. In addition, low-power design flow is enhanced with support for UPF-based IP models, advanced nested voltage islands (donut shapes), and multi-vendor UPF interoperability. The Olympus-SoC product now provides complete support for TSMC's iDRC, iRCX, iPRT, and iLPC formats, as well as enhanced DFM utilities applied during routing.
Also new in Reference Flow 11.0 is the Calibre InRoute manufacturing closure platform, which enables designers to natively invoke Calibre tools within the Olympus-SoC place and route system to achieve true manufacturing closure during physical design. A new Calibre Pattern Matching product integrated with Calibre InRoute and Olympus-SoC enables correct-by-construction design by recognizing and eliminating restricted layout patterns that can cause DRC/DFM violations.
The Calibre nmDRC, nmLVS, and xRC tools have been enhanced for TSMC's through-silicon via (TSV) offerings with new automation for verifying multi-die circuit implementations. In addition, the Calibre LFD tool now also supports TSMC's iLPC format.
For silicon test and diagnosis, the Tessent™ product line has expanded support for hierarchical test including enhanced at-speed scan test with both embedded compression and logic built-in self-test (BIST). Reference Flow 11.0 also includes new capabilities for comprehensive embedded memory BIST, and a complete boundary scan implementation flow.
"Mentor's complete system-to-silicon track in Reference Flow 11.0 allows us to address our mutual customers' biggest challenges for 28nm, especially managing the complexity of design from the system level all the way to IC implementation and testing," said Walden C. Rhines, chairman and CEO, Mentor Graphics. "Our close collaboration with TSMC allows us to close the loop between designers and foundries with tools that help our customers get their products to market faster with higher performance, lower power consumption and greater reliability."
About Mentor Graphics
Mentor Graphics Corporation (
(Mentor, Mentor Graphics, Catapult, Questa, 0-In, and Calibre are registered trademarks and Vista, Olympus-SoC and Tessent are trademarks of Mentor Graphics Corporation. All other company and/or product names are the trademarks and/or registered trademarks of their respective owners).
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For more information, please contact: Carole Dunn Mentor Graphics 503.685.4716 Email Contact Ry Schwark Mentor Graphics 503.685.1000 Email Contact
