Topics include System-Level Design, VMM Verification Methodology and a multi-tool IPL Flow Demonstration
WHO: The event is recommended for EDA tool developers, IC design engineers, and IP providers to discuss the industry-critical topics of interoperability and standards.
WHAT: The November 2009 Forum focuses on the latest developments in EDA interoperability with sessions dedicated to:
The Interoperable Process Design Kit (PDK) Libraries Alliance:
-- Demonstration by key IPL Alliance members showing a single 90nm generic
interoperable PDK supporting multiple vendor tools and flows including
schematic capture, simulation, layout editing, physical verification and
extraction
System-Level Design:
-- Hear the latest developments in SystemC(TM) TLM-2.0 through the
experiences of JEDA(TM) Technologies, Carbon Design Systems(TM) and
Tensilica.
VMM Verification Methodology:
-- Presentations from key VMM Catalyst program members on new features in
VMM for verification planning and VIP, verification of low power
designs, rapid testbench development and more. Attendees will receive a
copy of the Doulos(R) Golden Reference Guide for VMM.
The Forum, with this year's theme of "Peace, Love and Interoperability," also features the most recent advances in these key EDA standards: Liberty(TM) Library Modeling, IEEE Standard 1801(TM) for Low Power, and the HapsTrak(TM) standard for prototyping board connectors.
WHEN: Thursday, November 5th in Santa Clara, Calif. The Forum is open to all who wish to attend at no cost. Lunch and a light breakfast are included.
WHERE: The Sun Conference Center at Agnews Historic Park in Santa Clara, Calif. from 9:00am to 5:00pm. For more information, directions, and to register, visit: http://www.synopsys.com/Community/Interoperability/Pages/InteropForumNov09.aspx
About Synopsys
Synopsys, Inc. (NASDAQ: SNPS) is a world leader in electronic design automation (EDA), supplying the global electronics market with the software, intellectual property (IP) and services used in semiconductor design, verification and manufacturing. Synopsys' comprehensive, integrated portfolio of implementation, verification, IP, manufacturing and field-programmable gate array (FPGA) solutions helps address the key challenges designers and manufacturers face today, such as power and yield management, software-to-silicon verification and time-to-results. These technology-leading solutions help give Synopsys customers a competitive edge in bringing the best products to market quickly while reducing costs and schedule risk. Synopsys is headquartered in Mountain View, California, and has more than 65 offices located throughout North America, Europe, Japan, Asia and India. Visit Synopsys online at http://www.synopsys.com/.
Synopsys is a registered trademark of Synopsys, Inc. All other trademarks or registered trademarks mentioned in this release are the intellectual property of their respective owners.
Contact:
Sheryl Gulizia
Synopsys, Inc.
(650) 584-8635
sgulizia@synopsys.com
Lisa Gillette-Martin
MCA
(650) 968-8900, ext. 115
lgmartin@mcapr.com
Web site: http://www.synopsys.com/
