MUNICH & MOUNTAIN VIEW, Calif. — (BUSINESS WIRE) — July 29, 2009 —
A panel of EDA industry experts representing leading-edge companies and
world-renowned universities will address recent advances to ease and
speed property and design debugging, in a special session at this year’s
DAC. Debugging of RTL that failed verification is the largest manual
burden in chip design today. It takes 30 to 35% of the total design time
as it adds uncertainties and costs. A failure trace returned in
simulation, property checking and assertion-based methods is not enough
– leaving users with the question “Okay, where is the bug?” and an often
lengthy debugging session. Productivity is stymied until the bug is
found, often involving time-consuming iterations between verification
and design engineers. This special session chaired by Eli Singerman of
Intel Corp. and organized by Rolf Drechsler of the University of Bremen
will tackle such issues as tool advances to accelerate root cause
analysis of failures, automation in RTL and post-silicon debug, how
formal techniques can speed debugging, and RTL debugging techniques
based on information from higher abstraction levels. Six short papers
will be presented, and a half-hour interactive discussion will wrap up
the session.
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PANELISTS:
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Gila Kamhi, Principal Engineer, Intel
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Rajeev Ranjan, CTO, Jasper Design Automation
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Adriana Maggiore, Principal Application Engineer, OneSpin Solutions
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Masahiro Fujita, Professor, University of Tokyo
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Andreas Veneris, Professor, University of Toronto
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Valeria Bertacco, Professor, University of Michigan
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WHEN:
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Thursday, July 30, 2009, 9 - 11 a.m.
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WHERE:
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Moscone Center, Room 133
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747 Howard Street
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San Francisco, CA 94103
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WHY:
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Although verification is well understood and handled by many
automated approaches, debugging is fast becoming a bottleneck to
productivity. Come learn more from the experts about how to find
bugs efficiently.
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