What's New
SDL Router is an automatic routing engine integrated directly into Tanner EDA's Schematic Driven Layout (SDL) software. It speeds layout by automatically routing non-critical nets while allowing the designer to focus on routes that require expensive hand craftsmanship for performance or addressing analog-sensitive nets or parts of nets. The router is interactively controlled by a layout engineer. It natively uses the routing geometry created by the user, and runs on all or a specified subset of nodes on each pass. Users can manually route part of a net and have the router automatically finish routing the net. Because of the router's integration with Tanner EDA's SDL software, users can easily highlight and rip up nodes, manage the manual and automatic routing status, and implement Engineering Change Orders (ECOs).
DevGen, coupled with SDL, takes productivity to a new level. It allows analog layout designers to become more productive by automating much of the tedious task of laying out the devices. DevGen provides parameterized layout generators that are easily configured for any process to help ensure error-free layout. By using the DevGen wizard and answering a few questions about the layers involved and the Design Rule Checks (DRCs), designers can create parameterized cells of common devices without having to write code. DevGen includes layout generators for capacitors, resistors, inductors, MOSFETs, and diodes.
SDL Router and DevGen increase the speed and quality of custom layout and encourage good design practices by keeping close synchronization between the schematic and the layout. SDL improves productivity by automating instancing of cells and parameterized devices and placement quality by displaying real-time node flylines. It also helps avoid routing congestion and tracks an engineer's progress to help manage workflow.
Besides the new SDL Router and DevGen, version 14.10 of Tanner Tools Pro and HiPer Silicon includes new features that enhance productivity, including:
-- Improved Verilog-A integration to reduce analog simulations runtime,
when simulations include digital blocks.
-- HiPer Verify runs Calibre and Dracula foundry files natively, without
conversion or modification as well as Assura foundry files natively.
-- Safe Operating Area (SOA) checks in T-Spice so models stay valid and
circuits operate correctly.
-- Interactive DRC displays violations in real time during layout editing
that help layout engineers create compact, error-free layouts the first
time. The software displays the spacing distance in real time while the
layout is edited and can prevent editing from getting closer than the
minimum distance.
Price and Availability
Tanner EDA software is available now. Packages start at $25,000.
The products will be demonstrated at the Design Automation Conference, in San Francisco, July 27-30, 2009 at Tanner EDA's Booth #3655.
About Tanner EDA Software
Tanner Tools Pro is a software suite for the design, layout and verification of analog, mixed-signal, RF and MEMS ICs. It includes S-Edit for schematic capture, T-Spice for analog circuit simulation and L-Edit for physical layout. HiPer Silicon builds on the capabilities of Tanner Tools Pro with advanced features that improve designer productivity, including the HiPer Verify foundry-compatible physical verification engine, Verilog-A simulation, an interactive autorouter, and device layout automation. Tanner EDA software is available on the Windows® and Linux® platforms with flexible node-locked and networked licensing configurations.
About Tanner EDA
Tanner EDA is a leading provider of PC-based electronic design automation (EDA) software solutions for the design, layout and verification of analog and mixed-signal ICs and MEMS. Its solutions help speed designs from concept to silicon and are used by thousands of companies to develop devices cost-effectively in the biomedical, consumer electronics, next-generation wireless, imaging, power management, RF and photovoltaic market segments. Founded in 1988, Tanner EDA is a division of privately held Tanner Research, Inc.
Tanner EDA has been in the EDA market for over 20 years, and has shipped over 25,000 licenses of its PC-based electronic design software to more than 4,000 customers in 67 countries. For more information on Tanner EDA products, visit www.tannereda.com.
Notes to editors
Product graphics are available on request,
Acronyms: A/MS: Analog and Mixed Signal EDA: Electronic Design Automation PC: Personal Computer MEMS: Microelectromechanical Systems RF: Radio Frequency
Windows is a registered trademark of Microsoft Corporation in the United States and other countries.
Linux is a registered trademark of Linus Torvalds.
Tanner Tools Pro and HiPer Silicon are trademarks of Tanner Research, Inc.
All other trademarks and tradenames are the property of their respective owners.
Add to Digg Bookmark with del.icio.us Add to Newsvine
Press Contact: Georgia Marszalek ValleyPR LLC +1 650 345 7477 Email Contact
