UMC Qualifies Comprehensive Mentor Graphics Silicon Test Suite for its 65nm and 40nm IC Reference Flows

WILSONVILLE, Ore. — (BUSINESS WIRE) — June 23, 2009 Mentor Graphics Corporation (NASDAQ: MENT) today announced that its silicon test and diagnosis suite has been validated by UMC, a world leading semiconductor foundry, for use in its 65 and 40 nanometer reference flows. The foundation of this comprehensive silicon test flow is the TestKompress® automated test pattern generation (ATPG) solution for achieving high test quality with the lowest test cost. Complementing this scan test solution are Mentor’s MBISTArchitect™ for memory built-in self test (BIST), the BSDArchitect™ 1149.1-compatible boundary scan tool, and the YieldAssist™ failure diagnosis and yield monitoring tools.

“Mentor provides a very thorough testing solution for our 65 and 40nm processes,” said Stephen Fu, IP Development & Design Support Division Director at UMC. “Mentor’s test tools provide the complete manufacturing test flow that our customers require. With this flow we are able to provide them with test tools that match the advanced technology provided by our 65 and 40 nanometer process nodes. This takes the guesswork out of implementing a thorough manufacturing test.”

Complete Testing Flow Provides Advanced Testing Capabilities

The UMC flow provides a range of advanced capabilities addressing new requirements in testing advanced IC devices. The TestKompress product provides highly compressed test patterns supporting a wide variety of fault models including stuck-at, transition, multiple detect, and timing-aware delay. Power-aware features in the TestKompress product adjust test patterns to reduce total power dissipation during testing and to keep maximum power under a user-specified threshold.

The MBISTArchitect tool automates the process of providing at-speed testing of multiple instances of memory, while keeping area overhead to a minimum. The BSDArchitect tool is used for inserting boundary scan and TAP control for the memory BIST. The YieldAssist tools enable rapid diagnosis of failing devices to identify the location and type of defects, keeping IC yields high.

“Our complete set of silicon test tools are targeted at advanced IC technologies such as the 65 and 45 nanometer processes offered by UMC,” said Joe Sawicki, Vice President and General Manager of the Design-to-Silicon division at Mentor Graphics. “The UMC Reference Flow means that customers will have a fully verified test flow that can be applied to a wide variety of devices.”

Availability

The UMC 65nm and 40nm Reference Flow testing solution includes the MBISTArchitect, BSDArchitect, TestKompress, and YieldAssist products. All products are available now.

About Mentor Graphics

Mentor Graphics Corporation (NASDAQ: MENT) is a world leader in electronic hardware and software design solutions, providing products, consulting services and award-winning support for the world’s most successful electronics and semiconductor companies. Established in 1981, the company reported revenues over the last 12 months of about $800 million and employs approximately 4,425 people worldwide. Corporate headquarters are located at 8005 S.W. Boeckman Road, Wilsonville, Oregon 97070-7777. World Wide Web site: http://www.mentor.com/.

(Mentor Graphics and TestKompress are registered trademarks, and MBISTArchitect, BSDArchitect and YieldAssist are trademarks of Mentor Graphics Corporation. All other company or product names are the registered trademarks or trademarks of their respective owners.)



Contact:

Mentor Graphics
Gene Forte, 503-685-1193
Email Contact
or
Sonia Harrison, 503-685-1165
Email Contact

Featured Video
Jobs
Senior Firmware Architect - Server Manageability for Nvidia at Santa Clara, California
Design Verification Engineer for Blockwork IT at Milpitas, California
CAD Engineer for Nvidia at Santa Clara, California
GPU Design Verification Engineer for AMD at Santa Clara, California
Senior Platform Software Engineer, AI Server - GPU for Nvidia at Santa Clara, California
Sr. Silicon Design Engineer for AMD at Santa Clara, California
Upcoming Events
MEMS & Sensors Executive Congress (MSEC 2024) at Château-Bromont Hotel in Bromont Quebec Canada - Oct 7 - 9, 2024
PCB West 2024 at Santa Clara Convention Center Santa Clara CA - Oct 8 - 11, 2024
DVcon Europe 2024 at Holiday Inn Munich City Center, Munich Germany - Oct 15 - 16, 2024
International Test Conference (ITC) at United States - Nov 3 - 8, 2024



© 2024 Internet Business Systems, Inc.
670 Aberdeen Way, Milpitas, CA 95035
+1 (408) 882-6554 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy PolicyAdvertise