As a leading ASIC services company, Faraday has seen customers' designs increasing in complexity. This has resulted in a 3X average increase of design sizes over the past year. However, by using an integrated methodology based on the CPF-enabled Cadence Low-Power Solution, as well as adopting a platform-based design approach, Faraday was able to take on the increased design complexity and improve average design time by 20 percent over the course of the year. This trend was demonstrated consistently over a span of more than 20 low-power designs.
"The Cadence Low-Power Solution provides us with exactly what we need to produce a consistent and reliable flow for taping out low-power designs," said Kun-Cheng Wu, associate vice president of SoC & SiP Development and Service of Faraday Technology Corporation. "Leveraging the advanced technology in the Cadence Low-Power Solution, we now have a proven methodology providing the best power optimization design services for our customers worldwide."
"By being able to complete much larger designs in less time, with the added complexity of advanced low-power features, Faraday has shown that using the Cadence Low-Power Solution to optimize chip power consumption is the best way to go," said Steve Carlson, vice president of product marketing at Cadence Design Systems. "The phenomenal productivity results are a tribute to the union of great engineering and great engineering solutions."
The Cadence Low-Power Solution features critical technologies for power-efficient design, including the Encounter® Digital Implementation System and Conformal Low-Power. By using the Encounter Digital Implementation System for physical implementation, Faraday's design teams have access to native power domain support and integrated power signoff through Encounter Power System. In addition, Conformal Low-Power provides Faraday with pre-layout and post-layout functional and structural checking, ensuring correctness of the final silicon. Encounter Digital Implementation System and Conformal LP are integral parts of the CPF-enabled Cadence Low-Power Solution.
About Faraday Technology Corporation
Faraday Technology Corporation is a leading fabless ASIC and silicon IP provider. The company's broad silicon IP portfolio includes Cell Library, Memory Compiler, ARM-compliant CPUs, DDRI/II/III, MPEG4, H.264, USB 2.0/3.0, 10/100 Ethernet, Serial ATA, and PCI Express. With 2008 revenue of US$ 149 million, Faraday is one of the largest fabless ASIC companies in the Asia-Pacific region, and it also has a significant presence in other world-wide markets. Headquartered in Taiwan, Faraday has service and support offices around the world, including the U.S., Japan, Europe, and China. For more information, please visit: www.faraday-tech.com.
About Cadence
Cadence enables global electronic design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence software and hardware, methodologies, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry. More information about the company, its products, and services is available at www.cadence.com.
Cadence, Encounter and the Cadence logo are registered trademarks of Cadence Design Systems, Inc. in the United States and other countries. All other trademarks are the property of their respective owners.
Add to Digg Bookmark with del.icio.us Add to Newsvine
For more information, please contact: Dan Holden Cadence Design Systems, Inc. (408) 944-7457 Email Contact
