China's Academy of Sciences Adopts Cadence Incisive Xtreme III System to Validate Next-Generation Multi-Core Processor Designs

SAN JOSE, CA -- (MARKET WIRE) -- Jun 01, 2009 -- Cadence Design Systems, Inc. (NASDAQ: CDNS), the leader in global electronic design innovation, today announced that the Chinese Academy of Sciences Institute of Computing Technology (ICT) has adopted the Cadence® Incisive® Xtreme® III System for accelerating the development of RTL design with a verification flow for its next-generation 64 million-plus gates Loongson III advanced multi-core microprocessor.

The deployment of the Incisive Xtreme III System for developing the ICT's advanced 65- and 45-nanometer multi-core processor enabled ICT engineers to accelerate system-level verification while validating software operations. The Xtreme III System supported the ICT's goals of accelerating hardware/software development while reducing the risk of costly re-spins.

"The Xtreme III System has made a significant impact in accelerating our simulation runtime process by a factor of 860 times, and has made co-verification a predictable process for our next-generation Loongson III multi-core design," said Dr. Weiwu Hu, chief architect of the ICT's CPU division. "This Cadence technology has helped us improve overall productivity, predictability and quality of our Loongson III development."

Using Xtreme III, the ICT was able to accelerate simulation productivity and to find at least 10 critical system-level bugs that could only be exposed by running several billions of cycles in a system-level environment. The system enabled early access to a flexible, high-performance verification platform for hardware/software co-development and delivered powerful built-in productivity features such as hot-swap and VCD-on-Demand. These capabilities enabled ICT developers to quickly bring up the system and find system-level bugs more simply than through traditional debugging methods.

The ICT also used Xtreme III to augment their FPGA prototyping flow to thoroughly address the complexity of their next-generation multi-core microprocessors. Xtreme III fully automates compiling and partitioning, virtually eliminating pin limitations and timing issues commonly found in large-scale FPGA prototyping systems. The accelerated scalable verification flow provided by Xtreme III gave ICT engineers the required verification throughputs and ease of use while minimizing the effort required in debugging the design in a system-level environment.

"The ICT's experience with its Loongson III design is a perfect example of the great value hardware-based solutions like the Incisive Xtreme III System can deliver to companies seeking greater productivity, predictability and quality," said James Liu, Cadence general manager of China and Hong Kong.

The Cadence Incisive Xtreme series of high-performance, high-capacity accelerators/emulators speeds the functional verification of designs at the behavioral, RTL, and gate levels. Designed for multi-user, multi-site, multi-purpose systems, the Xtreme series integrates with the Incisive simulation environment to perform advanced verification planning and to drive coverage-based, metric-driven verification closure.

About Cadence

Cadence enables global electronic design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence software and hardware, methodologies, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry. More information about the company, its products, and services is available at www.cadence.com.

Cadence, the Cadence logo, Incisive and Xtreme are registered trademarks of Cadence Design Systems, Inc. in the United States and other countries. All other trademarks are the property of their respective owners.

Add to Digg Bookmark with del.icio.us Add to Newsvine

For more information, please contact:
Dean Solov
Cadence Design Systems, Inc.
408-944-7226

Email Contact


Featured Video
Jobs
Sr. Silicon Design Engineer for AMD at Santa Clara, California
Senior Firmware Architect - Server Manageability for Nvidia at Santa Clara, California
Design Verification Engineer for Blockwork IT at Milpitas, California
GPU Design Verification Engineer for AMD at Santa Clara, California
Senior Platform Software Engineer, AI Server - GPU for Nvidia at Santa Clara, California
CAD Engineer for Nvidia at Santa Clara, California
Upcoming Events
Phil Kaufman Award Ceremony and Banquet to be held November 6 at Hayes Mansion at Hayes Mansion 200 Edenvale Ave San Jose CA - Nov 6, 2024
SEMICON Europa 2024 at Messe München München Germany - Nov 12 - 15, 2024
DVCon Europe 2023 at Holiday Inn Munich – City Centre Munich Germany - Nov 14 - 15, 2024
SEMI MEMS & Imaging Sensors Summit, at International Conference Center Munich Germany - Nov 14, 2024



© 2024 Internet Business Systems, Inc.
670 Aberdeen Way, Milpitas, CA 95035
+1 (408) 882-6554 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy PolicyAdvertise