Synopsys IC Validator Adopted by NVIDIA for Sign-off Physical

Synopsys IC Validator Adopted by NVIDIA for Sign-off Physical Verification

IC Validator Delivers 20x Faster Physical Verification Using 25 CPUs

MOUNTAIN VIEW, Calif., May 11 /PRNewswire-FirstCall/ -- Synopsys, Inc. (NASDAQ: SNPS), a world leader in software and IP for semiconductor design and manufacturing, today announced that NVIDIA Corporation has adopted Synopsys' recently announced IC Validator physical verification solution. The IC Validator DRC/LVS solution has been specifically developed for advanced designs at 45 nanometers (nm) and below to offer in-design physical verification as well as signoff. As the inventor of the Graphics Processing Unit (GPU) and the world leader in visual computing technologies, NVIDIA designs multi-billion transistor processors that require the highest level of tool performance and productivity. By achieving near-linear scalability, such as the 20x speedup observed by NVIDIA using 25 CPUs, IC Validator provides accelerated time to tapeout.

"We continue to push design complexity to meet our customers' visual computing needs. To validate such large designs in a timely fashion, we require a high-performance, high-capacity physical verification engine. IC Validator demonstrated that we can verify our largest designs overnight using our standard hardware configurations," said James Chen, manager of VLSI technology at NVIDIA. "In addition, the flexibility offered by IC Validator's highly programmable language will help us customize design flows to improve productivity. Working closely with our foundry partners, we are deploying IC Validator for our designs."

IC Validator has been architected to address the challenges physical designers of complex designs at advanced process nodes face today. IC Validator delivers the high accuracy necessary for leading-edge process nodes, excellent scalability for efficient utilization of available hardware, superior ease-of-use for the physical designer, and high programmability for easier runset development. The solution deploys intelligent auto detection techniques to identify available hardware resources by taking advantage of existing compute job scheduler configurations. This includes configuring an intelligent mix of distributed processing and multithreading to provide the industry's best scalability without special hardware setup. For the runset writers and CAD managers, IC Validator offers a flexible programming language that can cut runset size from 2-10x, lowering the cost of setting up, maintaining and modifying the physical verification environment. Already in production at a world-leading IDM and qualified at leading foundries, IC Validator offers incremental capabilities, significant automation and innovative features such as DRC error classification, multi-user collaboration, customized reporting and on-the-fly error reporting.

"As a leading semiconductor company focused on cutting-edge designs, NVIDIA has repeatedly set the bar for physical verification tool performance, capacity and programmability," said Antun Domic, senior vice president and general manager, Implementation Group at Synopsys. "NVIDIA's adoption of IC Validator is a significant endorsement of its benefits and Synopsys' technology addressing the requirements for the industry's most advanced designs."

About Synopsys

Synopsys, Inc. (NASDAQ: SNPS) is the world leader in electronic design automation (EDA), supplying the global electronics market with the software, intellectual property (IP) and services used in semiconductor design and manufacturing. Synopsys' comprehensive, integrated portfolio of implementation, verification, IP, manufacturing and field-programmable gate array (FPGA) solutions helps address the key challenges designers and manufacturers face today, such as power and yield management, system-to-silicon verification and time-to-results. These technology-leading solutions help give Synopsys customers a competitive edge in bringing the best products to market quickly while reducing costs and schedule risk. Synopsys is headquartered in Mountain View, California, and has more than 60 offices located throughout North America, Europe, Japan, Asia and India. Visit Synopsys online at http://www.synopsys.com/.

Synopsys is a registered trademark of Synopsys, Inc. Any other trademarks or registered trademarks mentioned in this release are the intellectual property of their respective owners.

    Editorial Contacts:

    Sheryl Gulizia
    Synopsys, Inc.
    650-584-8635
    sgulizia@synopsys.com

    Lisa Gillette-Martin
    MCA, Inc.
    650-968-8900 ext. 115
    lgmartin@mcapr.com

Web site: http://www.synopsys.com/