SAN JOSE, Calif., March 16 /PRNewswire-FirstCall/ -- ISQED CONFERENCE -- Synopsys, Inc. (NASDAQ: SNPS), a world leader in software and IP for semiconductor design and manufacturing, today introduced Yield Explorer, a new yield management product that expedites the discovery and mitigation of yield limiters in leading-edge integrated circuits. When compared with traditional methods, Yield Explorer can accelerate the first-silicon debug time by an order of magnitude. Establishing seamless connectivity between design, simulation, manufacturing and test domains, Yield Explorer enables superior return on investment (ROI) by minimizing design re-spin through rapid and comprehensive capture of design-process-test interactions causing low yield.

Traditional yield management methods are centered on wafer and die-level data and do not offer an easy connection to design. These methods are also inadequate for leading- edge technology nodes due to the systematic yield limiters originating in design-process-test interaction. Users have been forced to devise lengthy, manual workarounds to move data between yield management and EDA tools.

"Yield Explorer enabled us to achieve a tenfold improvement in time to results when investigating the causes of test failures using our volume diagnostics approach," said Davide Appello, DfX technologies senior expert, at STMicroelectronics. "With Yield Explorer, we were able to rapidly isolate, prioritize and correct the significant design issues within the first batch of product chips. This helped us reach higher yields immediately on the next design spin. Additionally, Yield Explorer also allowed accurate electrical defectivity monitoring, which is a key enabler for prediction of quality excursions for our automotive products."

Yield Explorer offers several novel approaches to enable fast interactive analysis for yield engineers dealing with systematic yield limiters. The GUI is uniquely structured around a layout viewer for easy superposition of test failures on the corresponding layers of physical design. In addition to the wide range of analytical functions, users also benefit from the industry standard Tcl scripting environment built into the GUI. This environment can accommodate very large volumes of data with customer-specific data naming and content requirements. Its dynamically extendable data model provides a way of assimilating new types and formats of data without any loss of information or efficiency.

"The nanometer node yield challenges are largely a result of complex marginalities in the interaction between design, process and test. Our customers, fabless and IDM alike have stressed the need for bringing design information into yield analysis," said Howard Ko, senior vice president and general manager of the Silicon Engineering Group at Synopsys. "Yield Explorer is the only yield management tool that links all aspects of the design, manufacturing and test flows into a single data-bank. We are confident that Yield Explorer will impart far greater effectiveness and efficiency to the product engineering efforts across our wide customer base."

For more information on Yield Explorer, please visit: http://www.synopsys.com/Tools/Manufacturing/YieldManagement/YieldExplorer/Pages/default.aspx

About Synopsys

Synopsys, Inc. (NASDAQ: SNPS) is the world leader in electronic design automation (EDA), supplying the global electronics market with the software, intellectual property (IP) and services used in semiconductor design and manufacturing. Synopsys' comprehensive, integrated portfolio of implementation, verification, IP, manufacturing and field-programmable gate array (FPGA) solutions helps address the key challenges designers and manufacturers face today, such as power and yield management, software-to-silicon verification and time-to-results. These technology-leading solutions help give Synopsys customers a competitive edge in bringing the best products to market quickly while reducing costs and schedule risk. Synopsys is headquartered in Mountain View, California, and has more than 60 offices located throughout North America, Europe, Japan, Asia and India. Visit Synopsys online at http://www.synopsys.com/.

Synopsys is a registered trademark of Synopsys, Inc. Any other trademarks or registered trademarks mentioned in this release are the intellectual property of their respective owners.

    Editorial Contacts:

    Sheryl Gulizia
    Synopsys, Inc.
    650-584-8635
    sgulizia@synopsys.com

    Lisa Gillette-Martin
    MCA
    650-968-8900 x115
    lgmartin@mcapr.com

Web site: http://www.synopsys.com/