CEVA-XC(TM) DSP Architecture Exploits Modularized Vector Unit to Deliver Scalable, Software-Programmable Solution Targeting LTE, WiMAX and SDR Applications
(Logo: http://www.newscom.com/cgi-bin/prnh/20051010/CEVALOGO)
CEVA-XC is specifically designed to address the stringent power consumption, time-to-market and cost constraints associated with developing a high performance, next generation wireless communications processor. Utilizing an innovative scalable and modular architecture, CEVA-XC addresses the precise requirements of any 4G processor design, from handset terminals and mobile broadband modules through to wireless infrastructure equipment.
Single-engine, low-power architecture suits battery-powered terminals
Designed as a unified and coherent architecture supporting advanced wireless processing, CEVA-XC eliminates the need for heterogenic architectures composed of multiple wireless coprocessors or accelerators which increase cost, time-to-market and software design complexity in wireless SoCs. To further cope with the stringent power consumption requirements, the CEVA-XC core integrates an innovative Power Scaling Unit, supporting multiple clock and voltage domains and low power operating modes, allowing developers to meet power limitations while using a fully-programmable approach. These key ingredients are coupled with a complete Integrated Development Environment including an optimizing C compiler, emulators, ESL tools and comprehensive software libraries to further reduce the associated integration effort and costs.
Scalability delivers unrivalled performance for infrastructure applications
CEVA-XC builds upon the architecture of the CEVA-X(TM) DSP by incorporating up to four modular Vector Units into the CEVA-X framework to deliver processing power of up to 200 billion operations per second. This performance level enables CEVA-XC to support multiple LTE/WiMAX channels in a single core, surpassing any other DSP available today for wireless infrastructure applications.
"As the industry moves closer to mass deployment of 4G technologies such as WiMAX and LTE, software-defined processors are emerging as the basis for the next generation of wireless chipsets", said Will Strauss, founder and president, Forward Concepts. "With the CEVA-XC communications processor, CEVA has leveraged its strong background in wireless baseband to deliver a highly innovative, single-core DSP architecture offering breakthrough levels of performance and power consumption for programmable 4G modem design."
"To keep pace with the relentless growth in consumer demand for media- rich, bandwidth intensive content on-the-go, wireless handset and infrastructure designers require a flexible, yet power-efficient and cost- effective baseband solution for their next generation 4G chipsets," said Gideon Wertheizer, CEO of CEVA. "CEVA-XC delivers the performance and scalability to address the precise requirements of multi-standard 4G terminals or infrastructure equipment. With a unique single-core, programmable architecture, our latest DSP supports the emerging wireless standards in software and raises the industry bar in terms of power efficiency and performance for next generation wireless applications."
Strong heritage in developing DSP cores for wireless applications
In developing the CEVA-XC communications processor, CEVA has leveraged more than 20 years of experience in high-performance programmable DSP cores for portable applications. The CEVA-X DSP at the heart of the CEVA-XC architecture is one of the industry's leading DSPs deployed in HSDPA and WiMAX chips. Today, CEVA's DSP cores are shipping with four of the world's top five handset manufacturers; Nokia, Samsung, LG Electronics and Sony Ericsson.
CEVA-XC: A scalable and configurable architecture
CEVA-XC is CEVA's first DSP core dedicated for communications processing. This fully programmable architecture is optimized for the most demanding wireless applications, capable of handling LTE class 5 and WiMAX II complete transceiver paths on a single core, supporting the most aggressive profiles including multiple antennas schemes such as MIMO 4x4. To reach these performance levels, the CEVA-XC architecture incorporates 1, 2 or 4 Vector Units within the CEVA-X architecture. Each vector unit consists of a 256-bit SIMD engine using 3-way VLIW and a large array of 16 MAC, arithmetic, logic and shift units. An optimized instruction set handles the requirements of wireless modems, including matrix processing, MIMO detectors, filtering, complex data permutations and bit stream processing.
The CEVA-XC DSP offers full inherent DSP support, enabling efficient control and data flows for a wide range of DSP tasks and data types, both vectorizable and scalar. This use of a native DSP architecture enables powerful C-level compiler support and dramatically simplifies software development effort. The CEVA-XC architecture also offers a number of optional instruction sets which further enable designers to reach the optimal balance of performance and cost in their design.
CEVA-XC Key Features
* Native programmable DSP architecture, optimized for wireless
communication applications
o Up to 4 Vector Units, each a 256-bit SIMD engine using 3-way VLIW
o General Computation Unit, supporting general DSP and control
operations
o Complete memory subsystem including tightly coupled memories (TCM),
caches, emulation and profiling modules and AXI system interfaces
* Extremely powerful computation capabilities
o Up to 64 16x16-bit MAC operations, 128 16x8-bit MAC operations
o Up to 64 arithmetic and logic operations per cycle
o Up to 400 16-bit operations in a cycle
* Uniquely designed for baseband processing
o Comprehensive instruction set for most advanced maximum-likelihood
(ML) MIMO detectors
o High flexibility in operations and data using a unique SIMD
programming model with intra-vector permutation capabilities
o Configurable utilization of optional instruction sets for optimal
balance between performance and cost
* Ultra low power design optimized for mobile devices
o Up to four times more power efficient than general purpose DSPs
o System level Power Scaling Unit enables speed and voltage scaling at
high level of granularity, including processing units, memory
subsystem, TCM and caches
o Supports multiple power-down modes, minimizing both dynamic and
static power consumption
Development Tools and Support
As with all CEVA DSP cores, the CEVA-XC architecture is supported by a robust Software Development Tools that include an optimizing C-compiler, IDE, debugger, simulators and profiler. In addition, CEVA offers optimized DSP and communication libraries, to allow the licensee quick and easy application development. The development tools run on Windows, Solaris and Linux, and are supported by a worldwide customer service team. These development tools are well proven in the field by numerous licensees and partners.
To learn more about CEVA-XC, visit http://www.ceva-dsp.com/4G
Availability
CEVA-XC is currently available for licensing to select customers. For more information, contact Email Contact.
About CEVA, Inc.
Headquartered in San Jose, Calif., CEVA is a leading licensor of silicon intellectual property (SIP) platform solutions and DSP cores for mobile handsets, portable and consumer electronics. CEVA's IP portfolio includes comprehensive solutions for multimedia, HD audio, voice over packet (VoP), Bluetooth and Serial ATA (SATA), and a wide range of programmable DSP cores and subsystems with different price/performance metrics serving multiple markets. In 2008, CEVA's IP was shipped in over 300 million devices. For more information, visit
http://www.ceva-dsp.com/
