The massive increase in processing power required for next generation compute-intensive applications, including wireless communication, image processing and high definition video, has created a need for higher levels of signal processing performance. Altera's Accelerated Libraries for Catapult C Synthesis are the cornerstone of this unique design flow. The libraries enable the Catapult C Synthesis tool to perform ASIC-like optimizations and advanced, technology-aware scheduling for unique DSP macro IP found in the Altera's most advanced FPGA technologies. The result is designs that operate 50-80 percent faster than results previously achieved by any high level synthesis tool. These performance levels even surpass RTL synthesis tools, a unique accomplishment considering the ANSI C++ source is of a much higher abstraction than RTL.
The Catapult C/Altera DSP design solution is a C-to-RTL design flow that closely resembles the traditional DSP software programming flow. In both flows, algorithm designers develop a floating-point model of an algorithm, and then convert that to a fixed-point model, typically in C++. At this point in the traditional flow, software developers compile the C code for an off-the-shelf DSP. With the Catapult C/Altera flow, a hardware designer would use the Catapult C Synthesis tool with Altera's Accelerated Libraries to automatically create a DSP hardware implementation for an Altera FPGA. Unlike before, the hardware designer does not need to manually write the RTL code, worry about hand-coded errors, or re-write RTL code numerous times to find an architecture that delivers reasonable performance. The Catapult C/Altera solution automates the RTL creation process, delivering hardware performance with the flexibility of a DSP software programming flow.
"In addition to being deployed at designing high-end ASICs, Catapult C Synthesis offers numerous productivity advantages for designers who target FPGAs," said Simon Bloch, general manager, Design Creation and Synthesis Division, Mentor Graphics. "Working closely with Altera, we have learned how to deliver even greater advantages to FPGA designers. With this partnership, Altera and Mentor Graphics have given our customers a new, efficient choice for implementing high-performance DSP functionality in their next-generation designs."
"Adding our Accelerated Libraries to the Catapult C Synthesis Tool is another important step in our partnership with Mentor Graphics and provides our customers with improved productivity and increased functionality for their designs," said Udi Landen, vice president of software and IP engineering at Altera. "The performance improvements that can be realized with the tool further promote the move of adopting FPGAs in a growing number of high-performance DSP applications."
Altera Joins Catapult Silicon Vendor Partners Program
Altera has also joined the Catapult Silicon Vendor Partners (SVP) Program, which allows ASIC, FPGA, and semiconductor foundry companies to provide Catapult libraries to their customers. Under the terms of the program, Mentor Graphics and Altera have performed extensive testing to ensure the quality and reliability of Catapult libraries with Altera IP and FPGA technology. As a result, Altera's customers can expect increased efficiency and decreased risk when they use the Catapult C Synthesis tool to implement hardware in Altera FPGA technology.
About Mentor Graphics
Mentor Graphics Corporation (NASDAQ: MENT) is a world leader in electronic hardware and software design solutions, providing products, consulting services and award-winning support for the world's most successful electronics and semiconductor companies. Established in 1981, the company reported revenues over the last 12 months of over $825 million and employs approximately 4,300 people worldwide. Corporate headquarters are located at 8005 S.W. Boeckman Road, Wilsonville, Oregon 97070-7777. World Wide Web site: http://www.mentor.com/.
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