"These technologies augment Atrenta's solution, allowing our customers to perform accurate design analysis early in the design cycle. As a result, they are able to make their designs correct right from RTL phase, limit design costs, as well as, save design development time," said Bernard Murphy, Atrenta's chief technology officer.
US patent 6,876,934, "Method for Determining Fault Coverage from RTL Description," allows users to accurately predict the ultimate test coverage by analyzing the RTL.
US patent 6,993,733, "An Apparatus and Method for Handling of Multi-Level Circuit Design Data" enables the implementation of look-ahead design methodology by evaluating the high level RTL representation of a device. It quickly emulates the downstream implementation of the device, thus exposing potential implementation issues early in the design or manufacturing cycle.
US patent 7,076,748, "Method for Efficient Identification and Implementation of Clock Gating of Integrated Circuits," permits identification and implementation of clock gating in IC design to reduce dynamic power consumption.
US patent 7,073,146, "Automatic Assertion Generation for Functional Validation of Integrated Circuits" provides a method for automatically detecting unstable clock-domain crossings in IC design and making a stability determination for a clock-domain crossing based on satisfaction of a stability function.
US patent 7,152,216, "Method, System, and Computer Program Product for Automatic Insertion and Correctness Verification of Level Shifters in Integrated Circuits with Multiple Voltage Domains" enables automatic insertion and verification of level shifter modules used in integrated circuits (ICs).
About Atrenta
Atrenta is the leading provider of broad-based design analysis solutions based on industry standard SpyGlass(TM) technology. Atrenta's design analysis tools deliver early design closure by eliminating downstream design problems and iterative discoveries. This leads to improved predictability and efficiency in SoC design phases including RTL design, IP reuse, Verification, logical and physical implementation. Atrenta has over 100 customers including the world's top 10 semiconductor companies. Think Early Design Closure, Think Atrenta!
Visit www.atrenta.com to learn about our solutions for RTL analysis, RTL debug, RTL synthesis, lint checker, low power, power estimation, power management, Design for Test (DFT), constraints management, Timing Exception Verification (TXV), Clock Domain Crossings (CDC), formal verification, RTL Prototyping, design closure, Platform based Design (PBD), IP reuse, system level design, synthesis, simulation etc.
This press release contains forward-looking statements. Atrenta disclaims any obligation and does not undertake to update or revise the forward-looking statements in this press release.
Contact:
Atrenta
Krishna Uppuluri, Corporate Marketing, +1 408-453-3333
Email Contact
