As speed and complexity requirements for custom chips increase, developers need proven solutions they can trust. DDR2 interfaces are typically one of the most difficult technologies to get right the first time, due to the large number of signals, extremely tight timing and complex architectural design.
"While the individual components required to build a DDR2 memory interface are available, a complete solution requires significant system-level knowledge of DDR2 SDRAM operation as well as an understanding of package design considerations and signal integrity," said Prasad Subramaniam, vice president of Design Technology, eSilicon. "With our optimized 90nm DDR2 solutions, our customers are leveraging our design expertise as well as our portfolio of best-in-class, third-party IP to more easily and cost-effectively deliver their high-performance products."
eSilicon will offer a portfolio of DDR2 interfaces which integrate the company's proven Physical Interface (PHY) technology with solutions from its wide range of intellectual property (IP) partners, enabling end-to-end DDR2 memory interfaces that are optimized for specific applications. The first eSilicon(R) DDR2 interface to be offered targets high-performance computing applications and includes a DDR2 controller from Northwest Logic, DDR2 I/O technology from ARM, and Delay Locked Loop (DLL) IP from True Circuits, Inc.
The eSilicon PHY includes the timing-critical circuitry necessary to meet the precise requirements of a DDR2 SDRAM, including the capture logic, precision write logic, I/O buffers, I/O buffer calibration logic, and multiple settings for termination impedance and output driver impedance. Extensive DFT is included to fully support unit level production test; package design and simulation services are also available.
The eSilicon PHY provides a seamless interface to the Northwest Logic DDR2 SDRAM controller, one of the industry's smallest SDRAM solutions. This integration provides high data throughput and clock rates and full programmability of required timing. The controller, in combination with the PHY, provides many additional timing parameters not typically found in other controllers, to further ease integration. ARM(R) Artisan(R) DDR2 I/O technology enables a reliable, high-performance interface for signal integrity and noise reduction, and the DLL IP from True Circuits, Inc. enables high precision, low jitter clocking of the interface.
Availability
Optimized 90nm DDR2 interface solutions are available now from eSilicon. For more information about these products, or other solutions in the company's portfolio of semiconductor development solutions, contact a local eSilicon sales office or visit http://www.esilicon.com.
About eSilicon
eSilicon designs and manufactures custom integrated circuits for leading electronics companies. The company serves both system OEMs and fabless semiconductor companies who apply custom silicon to create innovative new products. eSilicon designs and ships custom chips for a wide variety of markets and applications, including high-volume MP3 players, home gateways, complex storage networks and high-speed communications devices.
Established in 2000 and led by a team of industry veterans, eSilicon is a pioneer and award-winning market leader, widely recognized for innovation and operational excellence. The company combines in-house design and manufacturing expertise to provide customers with a low-cost and lower-risk, path to best-in-class technology. eSilicon is headquartered in Sunnyvale, CA, with offices in Allentown, PA; Murray Hill, NJ; Shin Yokohama, Japan; and Bucharest, Romania. For more information, please visit http://www.esilicon.com.
eSilicon is a registered trademark of eSilicon Corporation. ARM is a registered trademark of ARM Limited. Artisan is a registered trademark of ARM Physical IP, Inc. All other trademarks are the property of their respective owners.
Contact:
eSilicon Corporation, Sunnyvale Julie Seymour, 408-616-4655 Email Contact or Wired Island, Ltd. Mike Sottak, 408-876-4418 Email Contact
