SAN FRANCISCO, CA -- (MARKET WIRE) -- Jul 18, 2006 -- Silistix, a provider of innovative software for on-chip communications solutions, will be demonstrating its self-timed chip interconnect, which provides power-dissipation and design-productivity improvements over traditional on-chip, clocked, synchronous bus architectures, at the Design Automation Conference (DAC).

Silistix will be exhibiting at DAC and presenting two demonstrations in Booth 1714. Each demonstration will feature CHAINworks™, a tool suite for the development of self-timed on-chip interconnect.

The first demonstration will show a functional design using self-timed interconnect generated using CHAINworks. This demo will let the observer view the asynchronous signaling of the self-timed fabric as data is transferred through the design, clearly showing the advantages of self-timed technology.

The second demonstration will show CHAINworks integrated with the CoWare Platform Architect and CoWare Model Designer ESL tools, showing how putting ESL tools into the design flow allows designers to identify and resolve system problems earlier in the design cycle.

Come by Booth 1714 to talk with David Fritz, Silistix CEO and see CHAINworks in action.

What: Demonstration of the CHAINworks tool suite for developing self-timed interconnect fabrics

Where: Design Automation Conference (DAC), San Francisco, CA, Silistix Booth #1714

When: July 24-27, 9AM-6PM Monday through Wednesday, 9AM-1PM Thursday

Contact:
Pat Corcoran
Cain Communications
503-284-1563

Email Contact

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