In the recently-introduced Z-RAM floating body memory cell, the conventional storage capacitor is replaced by the body capacitance of a SOI MOSFET. The charge stored in the floating body affects the device threshold voltage through the body effect and can be used to distinguish two states. This eliminates the need for a capacitor element, so the resulting memory cell structure is based solely on a single transistor. Therefore, Z-RAM memories can achieve five times the density of embedded SRAM and twice the density of embedded DRAM designs.
For the first time, new experimental work by ISi - presented in this IEEE paper co-authored by ISi's CTO Pierre Fazan and personnel from TI, Infineon, SOITEC and ATDF (a subsidiary of Sematech) - shows that good retention characteristics for a Z-RAM memory cell based on CMOS FinFET and Tri-Gate devices can be measured. This means that FinFET-based Z-RAM memories are manufacturable, enabling the production of very low cost DRAMs and eDRAMs for 45 and sub 45-nm generations.
Comments Pierre Fazan: "This summer the first silicon we received back from the foundry has successfully demonstrated our claims for the Z-RAM technology on SOI. This new work shows that the structure is highly scaleable and suitable for use in devices for the years ahead."
About Innovative Silicon
Incorporated in 2002, Innovative Silicon was founded to develop and commercialise Floating Body effect memory for SoC/MPU products used in diverse applications including handheld computers, games consoles, cellular communications devices, cameras. The company closed its first round of VC funding in 2003, taped out its first 90nm megabit Z-RAM memory in 2004 and completed 65nm designs in July 2005. The company is incorporated in the USA, with R&D in Lausanne, Switzerland.
www.z-ram.com
Contact:
Billings Europe Nick Foot, +44 1491636393 Email Contact or Innovative Silicon Inc. Mark-Eric Jones, +41 21 693 89 99 Email Contact
