Third generation Aries Smart DSP Retimers double bandwidth to 64GT/s per lane; now sampling silicon and boards to leading AI and Cloud infrastructure providers

SANTA CLARA, Calif. — (BUSINESS WIRE) — March 12, 2024 — Astera Labs, a global leader in semiconductor-based connectivity solutions for AI and cloud infrastructure, today announced the expansion of its widely deployed, field-tested Aries PCIe/CXL Smart DSP Retimer portfolio, to include a solution that delivers robust, low-power PCIe® 6.x and CXL® 3.x connectivity between next generation GPUs, accelerators, CPUs, NICs, and CXL memory controllers in data-centric systems.

New Aries 6 Retimers build upon the company’s widely deployed PCIe 5.0 Retimer portfolio and expands the Intelligent Connectivity Platform that is shipping to all major hyperscalers and AI platform providers.

As the first offering in Astera Labs’ PCIe 6.x portfolio, Aries 6 sets the stage for a smart PCIe 6.x connectivity backbone that is robust, scalable, and customizable.

Casey Morrison, Chief Product Officer, Astera Labs, said, "PCIe 6.x technology’s superior bandwidth is required to handle data-intensive workloads and to maximize utilization of AI accelerators, but the faster speeds introduce new signal integrity issues in hyperscale platforms. Aries Smart DSP Retimers have set the gold standard for addressing critical PCIe/CXL connectivity challenges with a solid track record of robust performance and seamless interoperability. We’re proud that our third generation of Aries Retimers with support for PCIe 6.x, PCIe 5.x, and CXL 3.x have now been sampled to leading AI and cloud platform providers.”

New Aries 6 Retimers for PCIe 6.x/CXL 3.x are the industry’s lowest power solution to achieve higher bandwidth and extended reach in complex AI and compute topologies:

• Industry’s lowest power Retimers (11W typical for PCIe 6.x 16-Lane configuration)
• Low-latency connectivity up to 64 GT/s per lane
• Leading signal integrity performance with 36dB@64G PAM4 SerDes and DSP customized for demanding AI server channels to ensure robust PCIe 6.x links
• Offered in multiple lane variants (16-Lane and 8-Lane) to support PCIe 6.x and PCIe 5.x applications
• Offered in multiple form-factors (silicon chips, Smart Cable Modules, and boards) for robust Chip-to-Chip, Box-to-Box, and Rack-to-Rack PCIe/CXL signal reach extension by up to 3x
• Seamless upgrade from second generation Aries 5 Retimers to third generation Aries 6 Retimers following industry standard footprints
• Extensive observability of link health for fleet management and platform level performance optimization with the enhanced COnnectivity System Management and Optimization Software (COSMOS) suite, featuring new in-band and out-of-band diagnostics

Robust interoperability is essential to support rapid PCIe 6.x adoption as the specification is complex and supports a diverse ecosystem of processors, devices, and applications. The Aries Smart DSP Retimer portfolio is rigorously tested in Astera Labs’ Cloud-Scale Interop Lab and in customer platforms to ensure seamless plug-and-play interoperability with leading PCIe ecosystem silicon providers. Astera Labs closely collaborates with prominent GPU and CPU providers such as AMD, Intel, and NVIDIA to minimize PCIe 6.x/CXL 3.x interoperation risk, lower system development costs, and reduce time-to-market.

Raghu Nambiar, Corporate Vice President, Data Center Ecosystems and Solutions, AMD said, “AMD data center products are at the center of the Generative AI rollout and our accelerator platforms are vital to delivering leadership performance for these demanding applications. Our close collaboration with Astera Labs on PCIe technologies ensures our customers’ platforms continue to meet the higher bandwidth connectivity requirements of next-generation AI and HPC workloads.”

Mohamed Awad, Senior Vice President and General Manager, Infrastructure Line of Business, Arm, said, “Arm is delivering the technology, innovation and ecosystem required to make the promise of AI a reality. Our collaboration with Astera Labs will be essential in ensuring higher performance connectivity for the new era of built-for-AI custom silicon solutions based on the Arm Neoverse compute platform.”

Zane Ball, Corporate VP, General Manager Data Center and AI Product Management, Intel, said, “PCIe 6.0 interconnects supporting 64 GT/s data speeds will enhance Intel’s latest platforms designed to run next generation AI workloads. We applaud Astera for their investment in PCIe 6/CXL 3.1 ecosystem and their contributions toward the development of Intel’s retimer supplemental specification, which will accelerate the rollout of Generative AI deployments at scale.”

Brian Kelleher, Senior Vice President of GPU Engineering, NVIDIA, said, “NVIDIA GPUs supercharge generative AI and HPC applications, but powerful data connectivity is required to maximize their throughput. Astera Labs’ new Aries Smart DSP Retimers with support for PCIe 6.2 will help enable higher bandwidth to optimize utilization of our next-generation computing platforms.”

Resources:

• Aries PCIe/CXL Smart DSP Retimers [Webpage]
• Introducing Aries 6 Smart DSP Retimers: First Look Demo [Video]

Visit Astera Labs at NVIDIA GTC 2024, March 18-21, San Jose Convention Center

Astera Labs will demonstrate its new Aries Smart DSP Retimers for PCIe 6.x/CXL 3.x in Booth #1828. Schedule to meet with Astera Labs experts and learn how its solutions enable critical connectivity for AI and cloud infrastructure.

About Astera Labs

Astera Labs is a global leader in purpose-built connectivity solutions that unlock the full potential of AI and cloud infrastructure. Our Intelligent Connectivity Platform integrates PCIe, CXL, and Ethernet semiconductor-based solutions based on a software-defined architecture that is both scalable and customizable. Inspired by trusted partnerships with hyperscalers and the data center ecosystem, we are an innovation leader of products that are flexible, interoperable, and reliable. Discover how we are transforming modern data-driven applications at www.asteralabs.com.

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Joe Balich
Joe.balich@asteralabs.com