Synopsys and TSMC Collaborate to Accelerate 2nm Innovation for Advanced SoC Design with Certified Digital and Analog Design Flows

SUNNYVALE, Calif., Sept. 25, 2023 — (PRNewswire) — Synopsys, Inc. (Nasdaq:  SNPS) today announced that its digital and custom/analog design flows are certified for TSMC's N2 process technology, enabling faster delivery of advanced-node SoCs with higher quality. Both flows are seeing strong momentum, with the digital design flow achieving multiple tape-outs and the analog design flow adopted for several design starts. The design flows, powered by the Synopsys.ai™ full-stack AI-driven EDA suite, deliver a significant lift in productivity.  Synopsys Foundation and  Interface IP in development for the TSMC N2 process will help reduce integration risk and speed time to market for advanced HPC, AI, and mobile SoCs. Additionally, Synopsys AI-driven design technologies, including Synopsys DSO.ai™, are enabled to fast-path the optimization of N2 design to improve the power, performance, and area.

"High quality-of-results and faster time to market for advanced SoC designs are hallmarks of TSMC's and Synopsys' longstanding collaboration," said Dan Kochpatcharin, head of Design Infrastructure Management Division at TSMC. "We work closely with our design ecosystem partners like Synopsys to deliver a full-spectrum of best-in-class solutions for TSMC's most advanced process technologies, providing our mutual customers a clear advantage in meeting the silicon demands of high-performance applications, along with a proven path to rapidly migrate their designs from node to node."

"The Synopsys digital and analog design flows for the TSMC N2 process represent a significant investment by Synopsys across the full EDA stack, helping designers jumpstart their N2 designs, differentiate their SoCs with increasingly better power, performance, and chip density, and accelerate their time to market," said Sanjay Bali, vice president of Strategy and Product Management for the EDA Group at Synopsys. "Our close collaboration with TSMC through every generation of TSMC's process technologies enables us to deliver unmatched EDA and IP solutions that customers need to innovate and strengthen their competitive advantage."

Efficient Reuse of Designs from Node to Node
The Synopsys analog flow enables efficient reuse of designs from node to node on TSMC advanced processes. As part of the certified EDA flows, Synopsys provides interoperable process design kits (iPDKs) and Synopsys IC Validator™ physical verification for full-chip physical signoff.

Availability
The certified EDA flows are available now.

Additional Resources

About Synopsys
Synopsys, Inc. (Nasdaq: SNPS) is the Silicon to Software™ partner for innovative companies developing the electronic products and software applications we rely on every day. As an S&P 500 company, Synopsys has a long history of being a global leader in electronic design automation (EDA) and semiconductor IP and offers the industry's broadest portfolio of application security testing tools and services. Whether you're a system-on-chip (SoC) designer creating advanced semiconductors, or a software developer writing more secure, high-quality code, Synopsys has the solutions needed to deliver innovative products. Learn more at  www.synopsys.com.

Editorial Contact:         
Kelli Wheeler  
Synopsys, Inc.  
(518) 248-0780
Email Contact
Email Contact

Cision View original content to download multimedia: https://www.prnewswire.com/news-releases/synopsys-and-tsmc-collaborate-to-accelerate-2nm-innovation-for-advanced-soc-design-with-certified-digital-and-analog-design-flows-301936772.html

SOURCE Synopsys, Inc.

Contact:
Company Name: Synopsys, Inc.
Financial data for Synopsys, Inc.

Featured Video
Jobs
Design Verification Engineer for Blockwork IT at Milpitas, California
Senior Platform Software Engineer, AI Server - GPU for Nvidia at Santa Clara, California
GPU Design Verification Engineer for AMD at Santa Clara, California
Senior Firmware Architect - Server Manageability for Nvidia at Santa Clara, California
Sr. Silicon Design Engineer for AMD at Santa Clara, California
CAD Engineer for Nvidia at Santa Clara, California
Upcoming Events
Phil Kaufman Award Ceremony and Banquet to be held November 6 at Hayes Mansion at Hayes Mansion 200 Edenvale Ave San Jose CA - Nov 6, 2024
SEMICON Europa 2024 at Messe München München Germany - Nov 12 - 15, 2024
DVCon Europe 2023 at Holiday Inn Munich – City Centre Munich Germany - Nov 14 - 15, 2024
SEMI MEMS & Imaging Sensors Summit, at International Conference Center Munich Germany - Nov 14, 2024



© 2024 Internet Business Systems, Inc.
670 Aberdeen Way, Milpitas, CA 95035
+1 (408) 882-6554 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy PolicyAdvertise