Extending Moore’s Law: CEA-Leti & Intel to Develop Atomically Thin 2D TMDs on 300mm Wafers Using Layer Transfer Technology for Future Transistor Scaling

Extending Moore’s Law: CEA-Leti & Intel to Develop Atomically Thin 2D TMDs on 300mm Wafers Using Layer Transfer Technology for Future Transistor Scaling

As We Are Relentlessly Pushing Moore’s Law, 2D TMD Material Is a Promising Option For Extending the Limits of Transistor Scaling’

GRENOBLE, France – June 19, 2023 – CEA-Leti and Intel today announced a joint research project to develop layer transfer technology of  two-dimensional transition-metal dichalcogenides (2D TMDs) on 300mm wafers with the goal to extend Moore’s Law beyond 2030.

2D-layered semiconductors, such as molybdenum- and tungsten-based TMDs, are promising candidates to extend Moore’s Law and ensure ultimate scaling of MOSFET transistors, because 2D-FETs provide innate sub-1nm transistor channel thickness. They are suitable for high-performance and low-power platforms due to their good carrier transport and mobility, even for atomically thin layers. In addition, their device body thickness and moderate energy bandgap lead to enhanced electrostatic control, and thus, to low off-state currents. 

These characteristics position 2D-FET stacked-nanosheet devices as a promising solution for transistor scaling beyond 2030, which will require high-quality 2D channel growth, adapted transfer and robust process modules. To that end, the multi-year project will develop a viable layer-transfer technology of high-quality 2D materials (grown on 300mm preferred substrates) to another device substrate for transistor process integration. Intel brings decades of R&D and manufacturing expertise to this project and CEA-Leti also provides bonding and transfer-layer expertise and large-scale characterization.

“As we are relentlessly pushing Moore’s Law, 2D TMD material is a promising option for extending the limits of transistor scaling in the future,” said Robert Chau, Intel Senior Fellow in Technology Development and Director of Intel Europe Research. “This research program focuses on developing a viable 2D TMD-based technology in 300mm for future Moore’s Law transistor scaling.”

Intel brings its prowess and expertise in semiconductor-and-packaging research and technology to work with European partners to develop Moore's Law innovations and advance microelectronics in Europe. In 2022, Chau relocated from the U.S. to Europe to lead Intel Europe Research and to drive the Intel’s R&D with partners on the continent. Intel and CEA-Leti have a long history of strong collaboration in semiconductor design, processes and packaging technology.

Most recently, they announced a research breakthrough in a new die-to-wafer bonding technology using a self-assembly process for future chip integration in June 2022. Chau, who visited CEA-Leti’s Grenoble headquarters on June 16 to emphasize the importance of their collaborations and the launch of the project, has been a strong supporter of multi-year research collaborations between the two entities.

CEA-Leti CEO Sebastien Dauvé said industry roadmaps show that 2D materials will be integrated in future microelectronic devices, and transfer capability in 300mm wafers will be key to that integration.

“Due to their high-growth temperature exceeding 700°C and high-quality growth on preferred substrates, it is difficult to stack 2D materials can hardly be deposited on a stack as usual thin layers. So transfer holds the most promise for integrating them in future devices, and CEA-Leti’s strengths in this context are its expertise and know-how in transfer development and characterization,” Dauvé said.

About CEA-Leti

Leti, a technology research institute at CEA, is a global leader in miniaturization technologies enabling smart, energy-efficient and secure solutions for industry. Founded in 1967, CEA-Leti pioneers micro-& nanotechnologies, tailoring differentiating applicative solutions for global companies, SMEs and startups. CEA-Leti tackles critical challenges in healthcare, energy and digital migration. From sensors to data processing and computing solutions, CEA-Leti’s multidisciplinary teams deliver solid expertise, leveraging world-class pre-industrialization facilities. With a staff of more than 1,900, a portfolio of 3,200 patents, 11,000 sq. meters of cleanroom space and a clear IP policy, the institute is based in Grenoble, France, and has offices in Silicon Valley and Tokyo. CEA-Leti has launched 76 startups and is a member of the Carnot Institutes network. Follow us on www.leti-cea.com and @CEA_Leti.

Technological expertise

CEA has a key role in transferring scientific knowledge and innovation from research to industry. This high-level technological research is carried out in particular in electronic and integrated systems, from microscale to nanoscale. It has a wide range of industrial applications in the fields of transport, health, safety and telecommunications, contributing to the creation of high-quality and competitive products.

For more information: www.cea.fr/english 

About Intel

Intel (Nasdaq: INTC) is an industry leader, creating world-changing technology that enables global progress and enriches lives. Inspired by Moore’s Law, we continuously work to advance the design and manufacturing of semiconductors to help address our customers’ greatest challenges. By embedding intelligence in the cloud, network, edge and every kind of computing device, we unleash the potential of data to transform business and society for the better. To learn more about Intel’s innovations, go to newsroom.intel.com and intel.com.

© Intel Corporation. Intel, the Intel logo and other Intel marks are trademarks of Intel Corporation or its subsidiaries. Other names and brands may be claimed as the property of others.

 

Press Contact                                                                                

Agency

Sarah-Lyle Dampoux

Email Contact

+33 6 74 93 23 47

 



Read the complete story ...
Featured Video
Jobs
GPU Design Verification Engineer for AMD at Santa Clara, California
Sr. Silicon Design Engineer for AMD at Santa Clara, California
Design Verification Engineer for Blockwork IT at Milpitas, California
Senior Firmware Architect - Server Manageability for Nvidia at Santa Clara, California
Senior Platform Software Engineer, AI Server - GPU for Nvidia at Santa Clara, California
CAD Engineer for Nvidia at Santa Clara, California
Upcoming Events
SEMICON Japan 2024 at Tokyo Big Sight Tokyo Japan - Dec 11 - 13, 2024
PDF Solutions AI Executive Conference at St. Regis Hotel San Francisco - Dec 12, 2024
DVCon U.S. 2025 at United States - Feb 24 - 27, 2025



© 2024 Internet Business Systems, Inc.
670 Aberdeen Way, Milpitas, CA 95035
+1 (408) 882-6554 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy PolicyAdvertise