In addition to the keynote address, Ventana will be engaging with attendees through panels, demos and presentations.
Tue., Dec. 13
10:15am — KEYNOTE: Balaji Baktha
12:05pm — FIRESIDE CHAT: RISC-V Readiness for Data Center Deployments - Balaji Baktha and Mark Himelstein, RISC-V International
1:15pm — DEMO: SmartNIC with OvS-DPDK on RISC-V - Kumar Sankaran, Ventana Micro Systems
3:55pm — PANEL: Building a Scalable RISC-V Software Ecosystem - John Hengeveld, Intel, with panelist Kumar Sankaran, Ventana Micro Systems
Wed., Dec. 14
11:05am — DEMO: Storage Acceleration with SPDK on RISC-V - Kumar Sankaran, Ventana Micro Systems
12:05pm — PRESENTATION: RISC-V Power and Performance Management - Andrew Jones & Sunil V L, Ventana Micro Systems Inc.
1:50pm — PRESENTATION: RISC-V Perf-Model: An Open Source Cycle Accurate Performance Model for Community-wide use - Knute Lingaard, SiFive & Arup Chakraborty, Ventana Microsystems
4:20pm — PRESENTATION: RISC-V Nested Virtualization - Anup Patel, Ventana Micro Systems Inc
Thu., Dec. 15
10:00am — TUTORIAL: Performance Tools - Knute Lingaard, SiFive & Arup Chakraborty, Ventana Microsystems
Headquartered in Cupertino, Ventana Micro Systems Inc. was founded in 2018 to revolutionize the processor market by offering high-performance, extensible and secure compute chiplets based on RISC-V's open architecture. Ventana is a Premier Member of RISC-V International and part of its Technical Steering Committee. To learn more about Ventana visit the Web, Twitter and LinkedIn.
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