Cadence’s New Flow Automates Custom/Analog Design Migration on TSMC Advanced Technologies

Highlights:

  • Companies to enable easy node-to-node migration for analog blocks with enhanced PDK across multiple FinFET processes to accelerate design closure
  • Early customers seeing more than 2.5X design cycle reduction on common analog blocks
  • Cadence Virtuoso design platform is optimized for design migration and automation of TSMC FinFET technologies

 

SAN JOSE, Calif. — (BUSINESS WIRE) — October 26, 2022 — Cadence Design Systems, Inc. (Nasdaq: CDNS) collaborated with TSMC to develop a node-to-node design migration flow built upon the Cadence® Virtuoso® design platform for custom/analog IC blocks that use TSMC’s advanced process technologies. The Cadence and TSMC R&D teams worked together to ensure the Virtuoso Schematic Editor and Layout Editor automatically migrate a source design on TSMC N5 and N4 process technologies to a new design on TSMC N3E process technology. Early analog design IP trials of the new migration flow showed that design time on common analog blocks was more than 2.5X faster compared with manual migration.

The Virtuoso Application Library Environment schematic migration solution, which is integrated into the Virtuoso design platform, automatically migrates a source schematic’s cells, parameters, pins and wiring from one process node to another technology. The target schematic is then tuned and optimized using the Virtuoso ADE Product Suite’s simulation environment and circuit optimization technology to verify the new schematic meets all necessary measurement targets.

The Virtuoso Layout Suite supports the reuse of existing layouts on a given process technology to quickly recreate a migrated layout on a new process technology, using custom place and route automation. Thanks to Virtuoso Layout Suite templates, TSMC’s analog-mapping technology and the routing technology in the Virtuoso design platform, designers can automatically recognize and extract groups of devices in an existing layout and apply templates to similar groups in the new layout.

“Through our continued collaboration with Cadence, we’re enabling our customers to improve productivity and accelerate design closure when performing node-to-node design migration of analog blocks within the Virtuoso design platform,” said Dan Kochpatcharin, Head of Design Infrastructure Management Division at TSMC. “Through the availability of our enhanced PDKs, we’re making it easy for our customers to easily migrate custom/analog blocks from one of our widely used processes to another and benefit from the power, performance, and area improvements of our latest technologies.”

“By working closely with TSMC, our customers now have access to the most sophisticated migration and custom/analog place and route automation capabilities within the Virtuoso design platform,” said Tom Beckley, senior vice president and general manager in the Custom IC, IC Packaging, PCB and System Analysis Group. “We’ve continuously collaborated with our mutual customers to understand their real-world design requirements. This new easy-to-use, node-to-node design migration technology addresses a key requirement for our customers’ most challenging custom analog designs.”

The Cadence Virtuoso design platform supports the Cadence Intelligent System Design strategy, enabling system-on-chip (SoC) design excellence. For more information on the Virtuoso design platform, please visit http://www.cadence.com/go/virtuosomigrationpr.

About Cadence

Cadence is a pivotal leader in electronic systems design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality. Cadence customers are the world’s most innovative companies, delivering extraordinary electronic products from chips to boards to complete systems for the most dynamic market applications, including hyperscale computing, 5G communications, automotive, mobile, aerospace, consumer, industrial and healthcare. For eight years in a row, Fortune magazine has named Cadence one of the 100 Best Companies to Work For. Learn more at cadence.com.

© 2022 Cadence Design Systems, Inc. All rights reserved worldwide. Cadence, the Cadence logo and the other Cadence marks found at www.cadence.com/go/trademarks are trademarks or registered trademarks of Cadence Design Systems, Inc. All other trademarks are the property of their respective owners.

Category: Featured



Contact:

Cadence Newsroom
408-944-7039
newsroom@cadence.com

Featured Video
Jobs
Senior Firmware Architect - Server Manageability for Nvidia at Santa Clara, California
GPU Design Verification Engineer for AMD at Santa Clara, California
Senior Platform Software Engineer, AI Server - GPU for Nvidia at Santa Clara, California
CAD Engineer for Nvidia at Santa Clara, California
Sr. Silicon Design Engineer for AMD at Santa Clara, California
Design Verification Engineer for Blockwork IT at Milpitas, California
Upcoming Events
Phil Kaufman Award Ceremony and Banquet to be held November 6 at Hayes Mansion at Hayes Mansion 200 Edenvale Ave San Jose CA - Nov 6, 2024
SEMICON Europa 2024 at Messe München München Germany - Nov 12 - 15, 2024
DVCon Europe 2023 at Holiday Inn Munich – City Centre Munich Germany - Nov 14 - 15, 2024
SEMI MEMS & Imaging Sensors Summit, at International Conference Center Munich Germany - Nov 14, 2024



© 2024 Internet Business Systems, Inc.
670 Aberdeen Way, Milpitas, CA 95035
+1 (408) 882-6554 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy PolicyAdvertise