Intel PIPE (PHY Interface for PCIE, SATA, USB3.1, DisplayPort and USB4) specification has been ubiquitous PHY interface for accelerating the design and verification of higher layer protocol stacks for more than 15 years. Since then, there have been numerous changes to meet the requirements of ever-evolving serial interface protocols. The most recent major changes include SerDes architecture and the low pin count interface.
SerDes architecture was introduced in Intel’s PIPE 5.0 specification to promote more general purpose and lightweight PHY designs by moving most of the protocol specific logic to the MAC layer. This enable seamless re-use of PHY designs across supported protocols of PCIe, SATA, USB3.1, DP and USB4. Specifically, for PCIe, SerDes architecture support is recommended for Gen5 and mandatory for Gen6 onwards. SerDes architecture with Low-pin count interface is an optimum solution with lower signal pins and optimized latencies. SerDes also facilitates bypass sync header mode which can be used to push more ‘meaningful’ data on link and increase bandwidth efficiency further. Design architects can take advantage of this feature specifically low latencies design requirements.
SerDes Architecture moves encoding/decoding, loopback, elastic buffer and polarity detection logic from PHY to MAC device. PHY SerDes design essentially has receiver detection, serializing/deserializing and clock recovery logic. Controller designs can be highly optimized with limited control and side-band information transmitted across PIPE interface. In addition, several time-insensitive message bus operations can be carried out concurrently with actual traffic transmission boosting effective bandwidth utilization. Interestingly, asymmetric link requirements can leverage newly introduced RxCLK and RxWidth signals, opening up new avenue for innovation.
Below are diagrams from Intel PIPE 6.0 specification highlighting the changes from Original Architecture to SerDes Architecture in representative transmitter and receiver blocks.
These are big changes from original architecture and introduces verification challenges for SerDes compliant PHY and MAC devices. Major challenge being PIPE data typically will not be aligned to Serdes byte boundaries e.g recovered COM symbol on RxData may contain some bits on Serdes byte 1 and other in Serdes byte 2 in 8b/10b or TxData when concatenated with Sync header is bound to be transmitted across two Serdes bytes etc.
Illustration above show visual depiction of data on SerDes link which is not only cumbersome to debug but might also hide serious interoperability issues among different IP vendors. Exhaustive testing would be recommended for both MAC and PHY designs supporting SerDes architecture for data sanity, electrical idle entry/exit conditions, polarity inversion, loopback etc.
Cadence’s proven PCIe Verification IP is upgraded compliant to Intel PIPE 6.0 specification to support SerDes Architecture and provide infrastructure to verify above-said scenarios. Also, Cadence’s PHY Verification IP catering to unique challenges of PHY design supports SerDes Arch which can be used for protocol agnostic traffic and score boarding across Serial-PIPE interface.
Specification References:
PCI Express® Base Specification Revision 6.0, Version 0.7
PHY Interface for the PCI Express, SATA,USB3.1, DisplayPort, and USB4 Architectures Version 6.0
More Information:
For more information on Cadence PCIe Verification IP, see
VIP for PCI Express
For more information on Cadence PHY Verification IP, see
VIP for PHY
