Benefits in higher density, speed and cost savings

19 May 2021 - Unisantis® Electronics Singapore Pte. Ltd., today unveiled the company’s developments in Dynamic Flash Memory (DFM)® technology, a leap forward in the industry’s search for alternatives to DRAM for future low-cost high-density embedded or standalone memory applications. DFM is able to offer faster speeds and higher density when compared to DRAM or other types of volatile memory.

DFM was presented this week for the first time at the 13th IEEE International Memory Workshop (IMW), by its inventors, Drs. Koji Sakui and Nozomu Harada from Unisantis. DFM was well received by the IMW’s Scientific Committee, for having demonstrated not only performance benefits but also for its strategy of having been developed as an easy-to-implement DRAM replacement. Dr. Sakui’s paper entitled “Dynamic Flash Memory with Dual Gate Surrounding Gate Transistor (SGT)”, was presented publicly on the 18th May.

DRAM is a volatile, capacitor-based, destructive-read form of memory – and its challenge has long been to continue packing in more storage for lower cost, without increasing power consumption. DFM takes a revolutionary approach to overcome limitations of conventional volatile memory such as DRAM, with its inherent short, regular and power-hungry refresh cycles, as well as destructive read processes.

DFM is also a type of volatile memory, but since it does not rely on capacitors it has fewer leak paths, it has no connection between switching transistors and a capacitor. The result is a cell design with the potential for significant increases in transistor density and, because it not only offers block refresh, but as a Flash memory it offers block erase -- DFM reduces the frequency and the overhead of the refresh cycle and is capable of delivering significant improvements in speed and power compared to DRAM.

 By utilizing TCAD simulation, Unisantis has proven DFM has a substantial potential to increase density 4X compared to DRAM. The scaling of DRAM has almost stopped at 16Gb, according to recent IEEE ISSCC (International Solid-State Circuits Conference) papers. Modelling DFM at 4F2 cell density shows how perfectly structured DFM is ( see 4F2 cell image here). The design and development of DFM means significant Gb/mm2 improvements, and today’s limits on DRAM (currently 16Gb) could immediately see increases to 64Gb memory using DFM’s radically enhanced cell structure.

Replacing DRAM is a major challenge for the industry, not only because DRAM today accounts for over 50% of the current market demand for memory (Yole Development, 2020). Forecasts also suggest the need for this type of low cost, high density DRAM by 2025 will continue to grow and exceed $100Bn. But technology challenges also lie ahead presented by some of the proposed replacements, including capacitor-less DRAM, ZRAM or simplistic GAA and Nanosheet approaches, all which have their own limitations compared to DFM.

Unisantis is a transformative semiconductor company, with a patented surround gate transistor (SGT) technology, a 3D transistor design which offers significant system design and performance advantages to the manufacturers of memory and image sensor semiconductors and is essential for the high-tech industry as it scales to very small nodes.

The company is built on a history of successes in the memory semiconductor market, having been established by Dr. Fujio Masuoka in Singapore in 2008 following his ground-breaking work in developing Flash memory at Toshiba. Dynamic Flash Memory was developed by Unisantis with the proven technological principles of SGT Technology building on that work and the company’s innovations, particularly in memory semiconductors.

Koji Sakui, Unisantis and co-inventor of DFM, commented “The memory industry has long-since accepted DRAM technology is nearing the end of its life, but its significant market means any replacement technologies must provide the right balance of performance, costs and future scalability. After significant internal research and testing, we are delighted to unveil DFM to the market as the leading long-term viable option to DRAM.”

Following today’s unveiling, the company is now seeking to further its own technical development, and in parallel, to testing and demonstrating the features and fuller potential of DFM externally with a series of memory and foundry partnerships.

Further details on DFM and the application of Unisantis SGT Technology will be shared at future events.

DFM Features

Illustrates density, size, scalability and reliability improvements of DFM

Cell structure

The design of DFM means significant Gb/mm2 improvements, and today’s limits on DRAM

DFM structure

Close up of image above: showing the SGT pillar structure used in DFM

Background information

DFM: not another ZRAM, and not an Emerging Memory

Attempts to develop DRAM without capacitors have been unsuccessful, as seen in ZRAM where the margins between 1 and 0 have been too narrow – both ZRAM and DFM approaches are Gain Cells but  in DFM the PL gate eliminates the FB (Floating Body), and with a significant increase in the “1” and “0” margin results in noticeably increased speeds and improvements in the reliability of the memory cell. It does this by using the PL (Plate Line) gate to ‘stabilize’ the FB (Floating Body) and by separating 1” Write and “0” Erase modes, allows for the widest possible margin – avoiding issues with noise and the fluctuation of the FB. The wide margin in DFM will offer other design benefits which Unisantis will be announcing in the near future.

Unlike the so-called ‘emerging memory technologies’ (MRAM, ReRAM, FRAM, PCM) DFM does not involve adding additional materials on top of a standard CMOS process – an approach that drives up the cost, prohibitively.

Learn more about our SGT Technology

The Unisantis vertical Surround Gate Transistor (SGT) Technology offers several key characteristics to the resulting circuit implementation:

• Improved area density, compared to planar and FinFET transistors
• Reduced leakage power, due to the strong electrostatic control of the surrounding gate to the transistor channel
• Optimization of the transistor width and length dimensions for the end application, whether high-performance or extremely low power dissipation