Accelerating Verification Component development with OSVVM Model Independent Transactions
Presenter: Jim Lewis, VHDL User, Designer, Verification Engineer, Trainer, OSVVM developer, and IEEE VHDL Chair
Thursday, December 10th, 2020
Verification components have become an essential part of a structured VHDL environment. In OSVVM we implement verification components as an entity and architecture. This provides RTL engineers with a familiar environment to create model behavior.
The objective of any verification framework is to make the Device Under Test (DUT) "feel like" it has been plugged into the board. Hence, the framework must be able to produce the same waveforms and sequences of waveforms that the DUT will see on the board.
