• Decoupling core-level configuration and chip-level resources eliminates compromises between DFT implementation effort and test cost.
• Samsung Foundry includes new Tessent Streaming Scan Network in reference flow.

Growing demand for next-generation integrated circuits (ICs) that deliver the extreme performance required for fast-evolving applications such as artificial intelligence and autonomous driving has resulted in an unprecedented increase in the size of IC designs, which today can integrate many billions of transistors. For IC engineering teams, larger IC design sizes and associated complexity translate to a dramatic rise in the time and cost required to test these massive IC designs, as well as the engineering effort needed to plan for and deploy design-for-test (DFT) structures and functionalities across each design.

To help silicon test teams address these challenges, Mentor, a Siemens business, today introduces Tessent™ Streaming Scan Network software for its Tessent™ TestKompress™ software. The new solution includes embedded infrastructure and automation that decouples core-level DFT requirements from the chip-level test delivery resources. This enables a no-compromise, bottom-up DFT flow that can dramatically simplify DFT planning and implementation, while reducing test time up to 4X. With full support for tiled designs and optimization for identical cores, it is ideal for increasingly large emerging compute architectures.

“The dramatic spike in IC test complexity due to increasing design sizes, advanced technology nodes, and use-model requirements presents significant challenges for IC design organizations,” said Brady Benware, vice president and general manager of Tessent Silicon Lifecycle Solutions for Mentor, a Siemens business. “With the Tessent Streaming Scan Network, our customers can be ready for the designs of tomorrow, while slashing test implementation effort and simultaneously optimizing manufacturing test cost today.”

Mentor’s new Tessent Streaming Scan Network is a bus-based scan data distribution architecture that enables simultaneous testing of any number of cores. It helps shorten test time by enabling high-speed data distribution, efficiently handling imbalances between cores, and supporting testing of any number of identical cores with a constant cost. It also provides a plug-and-play interface in each core that simplifies scan timing closure and is well-suited for abutted tiles.

The solution consists of a series of host nodes in each design block that are networked together. Each host distributes data between the network and the test structures in the block. The software automates the implementation, pattern generation, and failure reverse mapping processes. DFT engineers can fully optimize DFT test resources for each block without concern for impacts to the rest of the design. This helps to dramatically reduce the implementation effort. Along with optimized handling of identical cores, elimination of waste in the test data, and time multiplexing, this solution enables substantial reductions in test data time and volume.

“With the support for Tessent Streaming Scan Network technology in Tessent TestKompress, we are able to offer our customers a scalable test access solution ideal for today’s and tomorrow’s advanced IC designs,” said Sangyun Kim, vice president of Design Technology Team at Samsung Electronics. “We have found that the Tessent Streaming Scan Network significantly reduces the effort needed to make complex designs highly testable.”

The Tessent Streaming Scan Network capability in the Tessent TestKompress product is a result of more than 10 years of research and development in advanced hierarchical DFT implementation and test data bandwidth management. Mentor developed the technology in collaboration with multiple leading semiconductor manufacturers.

Tessent Streaming Scan Network is fully compatible with all other Tessent DFT products and can be combined with Tessent Diagnosis cell-aware and layout-aware diagnosis for a complete end-to-end defect detection and diagnosis solution. All Tessent DFT products are part of the Tessent Safe ecosystem and qualified for all ASIL ISO 26262 projects with a complete set of certified ISO 26262 documentation.

Mentor plans to showcase the Tessent Streaming Scan Network during the International Test Conference (ITC) held virtually November 3-5, 2020, www.itctestweek.org.

More information about Tessent Streaming Scan Network technology in the Tessent TestKompress product is available at www.mentor.com/tessent.

# # #

Contact for journalists

Jack Taylor

Phone: (512) 560-7143

E-mail: Jack_Taylor@mentor.com

Mentor Graphics Corporation, a Siemens business, is a world leader in electronic hardware and software design solutions, providing products, consulting services, and award-winning support for the world’s most successful electronic, semiconductor, and systems companies. Corporate headquarters are located at 8005 S.W. Boeckman Road, Wilsonville, Oregon 97070-7777. Website: http://www.mentor.com.

• Decoupling core-level configuration and chip-level resources eliminates compromises between DFT implementation effort and test cost.
• Samsung Foundry includes new Tessent Streaming Scan Network in reference flow.

Growing demand for next-generation integrated circuits (ICs) that deliver the extreme performance required for fast-evolving applications such as artificial intelligence and autonomous driving has resulted in an unprecedented increase in the size of IC designs, which today can integrate many billions of transistors. For IC engineering teams, larger IC design sizes and associated complexity translate to a dramatic rise in the time and cost required to test these massive IC designs, as well as the engineering effort needed to plan for and deploy design-for-test (DFT) structures and functionalities across each design.

To help silicon test teams address these challenges, Mentor, a Siemens business, today introduces Tessent™ Streaming Scan Network software for its Tessent™ TestKompress™ software. The new solution includes embedded infrastructure and automation that decouples core-level DFT requirements from the chip-level test delivery resources. This enables a no-compromise, bottom-up DFT flow that can dramatically simplify DFT planning and implementation, while reducing test time up to 4X. With full support for tiled designs and optimization for identical cores, it is ideal for increasingly large emerging compute architectures.

“The dramatic spike in IC test complexity due to increasing design sizes, advanced technology nodes, and use-model requirements presents significant challenges for IC design organizations,” said Brady Benware, vice president and general manager of Tessent Silicon Lifecycle Solutions for Mentor, a Siemens business. “With the Tessent Streaming Scan Network, our customers can be ready for the designs of tomorrow, while slashing test implementation effort and simultaneously optimizing manufacturing test cost today.”

Mentor’s new Tessent Streaming Scan Network is a bus-based scan data distribution architecture that enables simultaneous testing of any number of cores. It helps shorten test time by enabling high-speed data distribution, efficiently handling imbalances between cores, and supporting testing of any number of identical cores with a constant cost. It also provides a plug-and-play interface in each core that simplifies scan timing closure and is well-suited for abutted tiles.

The solution consists of a series of host nodes in each design block that are networked together. Each host distributes data between the network and the test structures in the block. The software automates the implementation, pattern generation, and failure reverse mapping processes. DFT engineers can fully optimize DFT test resources for each block without concern for impacts to the rest of the design. This helps to dramatically reduce the implementation effort. Along with optimized handling of identical cores, elimination of waste in the test data, and time multiplexing, this solution enables substantial reductions in test data time and volume.

“With the support for Tessent Streaming Scan Network technology in Tessent TestKompress, we are able to offer our customers a scalable test access solution ideal for today’s and tomorrow’s advanced IC designs,” said Sangyun Kim, vice president of Design Technology Team at Samsung Electronics. “We have found that the Tessent Streaming Scan Network significantly reduces the effort needed to make complex designs highly testable.”

The Tessent Streaming Scan Network capability in the Tessent TestKompress product is a result of more than 10 years of research and development in advanced hierarchical DFT implementation and test data bandwidth management. Mentor developed the technology in collaboration with multiple leading semiconductor manufacturers.

Tessent Streaming Scan Network is fully compatible with all other Tessent DFT products and can be combined with Tessent Diagnosis cell-aware and layout-aware diagnosis for a complete end-to-end defect detection and diagnosis solution. All Tessent DFT products are part of the Tessent Safe ecosystem and qualified for all ASIL ISO 26262 projects with a complete set of certified ISO 26262 documentation.

Mentor plans to showcase the Tessent Streaming Scan Network during the International Test Conference (ITC) held virtually November 3-5, 2020, www.itctestweek.org.

More information about Tessent Streaming Scan Network technology in the Tessent TestKompress product is available at www.mentor.com/tessent.