Highlights
- Portfolio of clocking, sensor, I/O and SERDES IP available on 32LP, 28LPP, 28FDSOI, 14LPP, 8LPP, 7LPP, 5LPE technologies to be presented at the Samsung Foundry SAFE Forum 2020 on October 28
- The challenges and requirements of AI chip design as well as application of SERDES technology in consumer and enterprise markets will be discussed, with a focus on the clocking, sensor, I/O and SERDES IP offered by Analog Bits
- Low power PLL
- PCIe reference clock
- Chip-to-chip I/O
- Clock TX/RX
- OSC pads
- PVT sensor
- Power supply glitch detector
- High lane count, low power, multi-protocol SERDES optimized for PCIe protocol
- PCI Express SERDES Markets Needs
- Consumer and Enterprise
- Analog Bits SERDES Capabilities and Application Use
- Low Power Full-Rate Architecture for Consumer Markets
- High Performance Half-Rate Architecture for Enterprise Market
- Silicon Results of PCIe Gen5
- Collaboration and IP Availability at Samsung
- Example of an AI Chip
- Challenges and Requirement Needs of AI Chips
- Capabilities Needed from Analog Foundation IPs
- Clocking
- Sensors
- IOs
- Analog Bits Analog Foundation IP offering in FinFET
- Partnership with Samsung
About Analog Bits Founded in 1995, Analog Bits, Inc. (
www.analogbits.com), is the leading supplier of mixed-signal IP with a reputation for easy and reliable integration into advanced SOCs. Products include precision clocking macros such as PLLs & Sensors programmable interconnect solutions such as multi-protocol SERDES and programmable I/O’s as well as specialized Sensors. With billions of IP cores fabricated in customer silicon, from 0.35-micron to 5-nm processes, Analog Bits has an outstanding heritage of "first-time-working” with foundries and IDMs. Editorial Contact: Hailey Carroll Analog Bits
haileyc@analogbits.com (650) 314-0200
