NSITEXE Accelerates Delivery of Data Flow Processor IP for Automotive and Industrial Applications Using the Cadence Digital Design Full Flow

Integrated Cadence digital design environment featuring the Genus Synthesis Solution lets NSITEXE reduce turnaround time by 75% and optimize overall PPA

SAN JOSE, Calif. — (BUSINESS WIRE) — July 11, 2019 — Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced that NSITEXE, Inc. deployed the Cadence® digital design full flow to accelerate the delivery of its high-efficiency, high-quality data flow processor (DFP) IP for automotive and industrial applications. Using the integrated Cadence digital full flow, starting with the Genus™ Synthesis Solution, NSITEXE successfully reduced turnaround time by 75% while also improving power by 8.5%, performance by 35% and reducing area by 3.5% when compared with its previous competitive solution. For more information on the Cadence digital full flow, please visit http://www.cadence.com/go/fedffnpr.

The Cadence flow deployed at NSITEXE included the Genus Synthesis Solution, Joules RTL Power Solution, Conformal® Equivalence Checker, Modus DFT Software Solution and Innovus Implementation System. The tightly integrated flow provided NSITEXE with a common Cadence database and user interface (UI), eliminating the need for data transfer between tools and communication exchanges between multiple engineers.

The Genus Synthesis Solution played a critical role in the flow, enabling NSITEXE to accelerate iterations from register-transfer level (RTL) to layout. Additionally, the shared engines between the Genus Synthesis Solution and the Innovus Implementation System helped NSITEXE avoid unnecessary iterations and identify design bottlenecks.

“To accelerate the delivery of our high-efficiency, high-quality DFP IP, we needed a solution that enabled us to achieve our aggressive turnaround time goals,” said Hideki Sugimoto, CTO of NSITEXE. “After an extensive evaluation, we decided to implement the Cadence full flow because it offered a tightly integrated design environment that created efficiencies for our team and produced optimal PPA results. We plan to use the Cadence flow to advance our next-generation IP for the rapidly evolving automotive and industrial markets.”

The Cadence digital design full flow is part of the broader digital and signoff suite, which provides customers with an integrated full flow, delivering better predictability and a faster path to design closure. It supports Cadence’s Intelligent System Design strategy, accelerating SoC design excellence.

NSITEXE will share more details about their experience with the Cadence digital design full flow at CDNLive Japan 2019, which will take place on July 19, 2019 in Yokohama, Japan. For more information on CDNLive Japan and to register, please visit www.cadence.com/go/cdnlivejapanpr.

About Cadence

Cadence enables electronic systems and semiconductor companies to create the innovative end products that are transforming the way people live, work and play. Cadence’s software, hardware and semiconductor IP are used by customers to deliver products to market faster. The company’s Intelligent System Design strategy helps customers develop differentiated products—from chips to boards to intelligent systems—in mobile, consumer, cloud data center, automotive, aerospace, IoT, industrial and other market segments. Cadence is listed as one of Fortune Magazine's 100 Best Companies to Work For. Learn more at cadence.com.

© 2019 Cadence Design Systems, Inc. All rights reserved worldwide. Cadence, the Cadence logo and the other Cadence marks found at www.cadence.com/go/trademarks are trademarks or registered trademarks of Cadence Design Systems, Inc. All other trademarks are the property of their respective owners.



Contact:

For more information, please contact:
Cadence Newsroom
408-944-7039
Email Contact

 

Featured Video
Jobs
Senior Firmware Architect - Server Manageability for Nvidia at Santa Clara, California
GPU Design Verification Engineer for AMD at Santa Clara, California
CAD Engineer for Nvidia at Santa Clara, California
Sr. Silicon Design Engineer for AMD at Santa Clara, California
Design Verification Engineer for Blockwork IT at Milpitas, California
Senior Platform Software Engineer, AI Server - GPU for Nvidia at Santa Clara, California
Upcoming Events
Phil Kaufman Award Ceremony and Banquet to be held November 6 at Hayes Mansion at Hayes Mansion 200 Edenvale Ave San Jose CA - Nov 6, 2024
SEMICON Europa 2024 at Messe München München Germany - Nov 12 - 15, 2024
DVCon Europe 2023 at Holiday Inn Munich – City Centre Munich Germany - Nov 14 - 15, 2024
SEMI MEMS & Imaging Sensors Summit, at International Conference Center Munich Germany - Nov 14, 2024



© 2024 Internet Business Systems, Inc.
670 Aberdeen Way, Milpitas, CA 95035
+1 (408) 882-6554 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy PolicyAdvertise