The two-day Workshop will feature more than 40 presentations from RISC-V Foundation members

ZURICH — (BUSINESS WIRE) — April 30, 2019 — RISC-V Foundation:

WHERE: ETH Zurich, Gloriastrasse 35, CH 8092 Zurich, Switzerland

WHEN: Tuesday, June 11 to Thursday, June 13, 2019

WHAT: The RISC-V Workshop Zurich will showcase the open, expansive and international RISC-V ecosystem. The event will highlight current and prospective projects and implementations that influence the future evolution of the free and open RISC-V instruction set architecture (ISA), with a focus on the momentum and growth of the RISC-V Foundation across Europe and beyond.

The event will feature two full days of presentations and updates on the RISC-V architecture, commercial and open-source implementations, software and silicon, vectors and security, applications and accelerators, simulation infrastructure and much more. RISC-V Foundation members presenting at the Workshop include: AdaCore, CEA, CloudBEAR, Dover Microsystems, Draper Labs, Embecosm, ETH Zurich, Hex Five Security, Huawei, Microchip Technology, OneSpin Solutions, Princeton University, Qamcom Research & Technology, Rambus, SiFive, Syntacore and Western Digital. The third day of the event will feature meetings for RISC-V Foundation members.

Tuesday, June 11, 2019:

• Guiding the Future of RISC-V
  • When: 9:00 – 09:15 CEST
  • Who: Calista Redmond, RISC-V Foundation
• Energy Efficient Computing from Exascale to MicroWatts: The RISC-V Playground
  • When: 9:15 – 09:40 CEST
  • Who: Luca Benini, ETH Zurich
• RISC-V State of the Union
  • When: 9:40 – 10:05 CEST
  • Who: Krste Asanovic, UC Berkeley and SiFive
• RISC-V Technical Committee Update
  • When: 10:05 – 10:20 CEST
  • Who: RISC-V Foundation
• RISC-V Marketing Committee Update
  • When: 10:20 – 10:35 CEST
  • Who: Ted Marena, RISC-V Foundation and Western Digital
• OpenPiton+Ariane: The First Linux-Booting Open-Source RISC-V Manycore
  • When: 11:30 – 11:45 CEST
  • Who: Jonathan Balkind, Princeton University; Michael Schaffner, ETH Zurich
• efabless' Raven: PicoRV32 on an ASIC, Open Source, Open Silicon
  • When: 11:45 – 12:00 CEST
  • Who: Tim Edwards and Mohamed Kassem, efabless Corporation
• PULP-NN: An Open-Source Library for Deeply-Embedded and Quantized Neural Networks (QNNs) on a RISC-V Based Parallel Ultra Low Power Cluster
  • When: 12:00 – 12:15 CEST
  • Who: Angelo Garofalo, University of Bologna; Luca Benini, ETH Zurich
• Bit by bit - How to fit 8 RISC-V Cores in a $38 FPGA board
  • When: 12:15 – 12:30 CEST
  • Who: Olof Kindgren, Qamcom Research & Technology
• OpenSBI Deep Dive
  • When: 13:30 – 13:55 CEST
  • Who: Anup Patel, Western Digital
• Secure Bootloader for RISC-V
  • When: 13:55 – 14:10 CEST
  • Who: David Garske and Daniele Lacamera, wolfSSL Inc.
• An Open Source Approach to System Security
  • When: 14:10 – 14:25 CEST
  • Who: Helena Handschuh, RISC-V Foundation and Rambus
• 60 Second Poster Preview Sessions
  • When: 14:25 – 14:50 CEST
• PolarFire SoC: a Secure, Low Latency Heterogeneous Compute Platform for the Edge
  • When: 15:20 – 15:45 CEST
  • Who: Ted Speers, Microchip Technology
• CHIPS Alliance – an Open Hardware Group
  • When: 15:45 – 16:00 CEST
  • Who: Yunsup Lee, SiFive
• PULP Platform: What's Next?
  • When: 16:00 – 16:15 CEST
  • Who: Frank Gürkaynak, ETH Zurich
• Bridging the Gap in the RISC-V Memory Models
  • When: 16:15 – 16:30 CEST
  • Who: Stefanos Kaxiras, Uppsala University and Eta Scale AB; Alberto Ros, University of Murcia and Eta Scale AB
• The First Space-Qualified Klessydra RISC-V Microcontroller to be Launched on a Satellite
  • When: 16:30 – 16:45 CEST
  • Who: Mauro Olivieri, Sapienza University of Rome and Barcelona Supercomputing Center; Luigi Blasi and Francesco Vigli, Sapienza University of Rome
• What You Simulate is What You Synthesize: Design of a RISC-V Core from C++ Specifications
  • When: 16:45 – 17:00 CEST
  • Who: Simon Rokicki and Olivier Sentieys, INRIA
• Updates from RISC-V Foundation Working Groups
  • When: 17:00 – 18:00 CEST
  • Who: RISC-V Foundation