Workshop features more than 25 speaking sessions and a keynote from Andes Technology

(BUSINESS WIRE) — March 11, 2019 — WHERE: Ambassador Hotel, No. 188號, Section 2, Zhonghua Rd, East District, Hsinchu City, Taiwan Region 30060

WHEN: Tuesday, March 12 to Wednesday, March 13, 2019

WHAT: The RISC-V Workshop Taiwan Region will showcase the open, expansive and international RISC-V ecosystem, highlighting current and prospective projects and implementations that influence the future evolution of the RISC-V instruction set architecture (ISA), with a focus on the growth of the RISC-V ecosystem across China and Asia.

The event will feature a variety of speaking sessions, along with poster presentations and demonstrations. RISC-V Foundation member companies presenting at the Workshop include: Andes Technology; Codasip; Cryptape Technology; Hex Five Security; MediaTek; Microsemi, a wholly owned subsidiary of Microchip Technology Inc.; Nuclei System Technology; SiFive; Software Hardware Consulting (SH Consulting); Syntacore; and Western Digital. Andes Technology will present the keynote on Tuesday, March 12. The event schedule is as follows:

Tuesday, March 12, 2019:

• Welcome & Foundation Overview
  • When: 08:30 – 08:45
  • Who: Rick O’Connor, RISC-V Foundation
• Keynote: Andes Technology
  • When: 08:45 – 09:10
  • Who: Andes Technology
• Panel: Opportunities & Challenges in AIoT
  • When: 09:15 – 10:00
  • Who: Frankwell Lin, Andes Technology; Steve Lo, Egis Technology Corp; Ted Speers, Microchip Technology; Chen-Yi Lee, National Chiao-Tung University; Zvonimir Bandic, Western Digital
• RISC-V Technical Committee Update
  • When: 10:30 – 10:45
  • Who: RISC-V Foundation
• RISC-V Marketing Committee Update
  • When: 10:45 – 11:00
  • Who: Ted Marena, RISC-V Foundation Marketing Committee and Western Digital
• Status Update of RISC-V P extension task group
  • When: 11:00 – 11:15
  • Who: Chuan-Hua Chang , Andes Technology
• Simulation Evaluation of Chaining Implementation for the RISC-V Vector Extension
  • When: 11:15 – 11:40
  • Who: Zhen Wei and Wei-Chung Hsu, National Taiwan University
• RISC-V Segmentation Extension Proposal
  • When: 13:00 – 13:15
  • Who: Wuyang Chung, Freelancer
• MediaTek RISC-V Processor on Sensorhub Application
  • When: 13:15 – 13:40
  • Who: Jeremy Liu, MediaTek
• New Members of AndeStar V5 Processor IPs
  • When: 13:45 – 14:10
  • Who: Charlie Su, Andes Technology
• Our Passion on the Popularization of RISC-V
  • When: 14:15 – 14:40
  • Who: Tony Xu, Nuclei System Technology
• Platform Security – A Detailed Comparison of RISC-V to Arm's TrustZone
  • When: 15:10 – 15:35
  • Who: Don Barnetson, Hex Five Security
• Cryptospec: a Trust Module System for 64-bit RISC-V Core Complex
  • When: 15:40 – 16:05
  • Who: Shumpei Kawasaki, SH Consulting; Cong-Kha Pham, University of Ellectro-Communication
• Energy-Efficient Face Detection Using Andes RISC-V Processor
  • When: 16:10 – 16:25
  • Who: Chien-Hao Chen and Po Yu Huang, National Chiao Tung University (NCTU)
• A Different World: a Blockchain-Focused, General-Purpose Applicable Software Sandbox System Based on RISC-V
  • When: 16:25 – 16:50
  • Who: Xuejie Xiao, Cryptape Technology
• Enabling TVM on RISC-V Architectures with SIMD Instructions
  • When: 16:55 – 17:20
  • Who: Allen Lu, Peakhills Group Corporation; Jenq-Kuen Lee, National Tsing-Hua University
• Poster Preview Sessions
  • When: 17:25 – 17:40