SAN JOSE, Calif. — (BUSINESS WIRE) — January 16, 2019 — Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced plans to showcase many of its latest solutions at DesignCon 2019 in Santa Clara, Calif., from January 29 to January 31, 2019. Exhibiting in booth 711, Cadence will demonstrate the capabilities of its Sigrity™ signal and power integrity solutions (SI/PI), multi-gigabit SerDes analysis, advanced DDR IP and design/analysis tools, automated IBIS-AMI model creation and advanced IC packaging and cross-platform solutions. To learn more about the Cadence activities at DesignCon and register for the conference, visit www.cadence.com/go/designcon2019.
WHAT: Cadence experts are scheduled to discuss new developments in these technologies and how they can help solve today’s SI challenges during the following tutorials, panels and sessions:
- Tutorial: Advanced IBIS-AMI Techniques for 32GT/s and Beyond, Tuesday, January 29 at 9:00 a.m., presented by Cadence and IBM
- Tutorial: Lowering the Barrier to Entry for Electronic/Photonic ICs, Tuesday, January 29 at 9:00 a.m., presented by Cadence, Lumerical and TowerJazz
- Panel: Photonics Coming of Age: The Emergence of PDKs, Tuesday, January 29 at 4:45 p.m., presented by Cadence, Lumerical, Mentor, TowerJazz, Hewlett Packard Enterprise and SMART Photonics
- Panel: Which Model When? Succeeding with IBIS-AMI, Thursday, January 31 at 3:45 p.m., presented by Cadence, SiGuys, Signal Integrity Software, Inc., Intel and Micron Technology
- Panel: Real-World Cloud and Machine Learning/AI Deployment for Hardware Design, Wednesday, January 30 at 3:45 p.m., presented by Cadence, Hewlett Packard Enterprise, Ansys, Intel and Synopsys
- Session: Mode Conversion and Its Impact on 112Gbps PAM4 Systems, Wednesday, January 30 at 8:00 a.m., presented by Cadence and Xilinx
- Session: Design Space Exploration with Polynomial Chaos Surrogate Models for Analyzing Large System Designs, Wednesday, January 30 at 9:00 a.m., presented by Cadence and Georgia Institute of Technology
- Session: Effect of Power Plane Inductance on Power Delivery Networks, Wednesday, January 30 at 9:00 a.m., presented by Cadence, Oracle and Samtec
- Session: Modeling and Simulation Challenges for 16Gbps GDDR6 Interfaces, Thursday, January 31 at 8:05 a.m., presented by Cadence
- Session: A Case Study on Analyzing LPDDR4X Interfaces Using Circuit and Channel Simulation, Thursday, January 31 at 9:05 a.m., presented by Texas Instruments
- Session: Exposing Adaptive Equalization Functionality in 32Gbps SerDes Receivers, Thursday, January 31 at 10:05 a.m., presented by IBM
- Session: A Case Study on Streamlining the DC Analysis Workflow, Thursday, January 31 at 11:05 a.m., presented by Google
- Session: Modeling and Simulating 112G SerDes, Thursday, January 31 at 2:00 p.m., presented by Cadence
- Session: Advanced Package Design Signoff Reference Flow, Thursday, January 31 at 2:50 p.m., presented by Samsung Foundry
- Session: System Planning and Management for 3D Designs, Thursday, January 31 at 3:45 p.m., presented by Cadence
The following demonstrations are also scheduled for the show:
- Thermal-aware PI design and analysis including multi-level tree-topology set-up from PCB schematics
- Power-aware SI analysis of next-generation GDDR and LPDDR interfaces using IBIS-AMI models
- Streamlining multi-gigabit SI and 3D interconnect extraction across PCB-connector interfaces for TX-to-RX interface compliance
- Advanced packaging and cross-platform solutions for next-generation 2.5D and 3D-IC design
- 112G long-reach SerDes for next-generation datacenter applications
Additionally, Cadence and Lumerical plan to deliver a brief update, “Shedding Light on Photonic Design,” highlighting enhancements to the electronic-photonic design automation (EPDA) flow at the Cadence booth on Wednesday, January 30, at 1:00 p.m.
WHEN: DesignCon is scheduled for January 29 – 31, 2019.
WHERE: Santa Clara Convention Center, 5001 Great America Parkway, Santa Clara, Calif. Cadence is in booth 711.
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