Open-Silicon to Demonstrate and Present on Custom SoC Platform Solutions for AI Applications at the TSMC OIP Event in Santa Clara

October 7, 2018 -- Open-Silicon, a system-optimized ASIC solution provider and long-standing member of TSMC’s  Value Chain Aggregator (VCA) and Design Center Alliance (DCA) programs, will present on custom SoC platform solutions for AI applications at the TSMC Open Innovation Platform® (OIP) Ecosystem Forum on October 3 in Santa Clara, CA. The company will also demonstrate its comprehensive High Bandwidth Memory (HBM2) IP subsystem solution for 2.5D ASICs in TSMC’s FinFET and CoWoS® technologies.  

What:

Custom SoC Platform with IP Subsystems Optimized for FinFET Technologies Enabling AI Applications

Advances in computing power and deep learning have enabled AI to reach a tipping point toward major disruption and rapid advancement. However, these applications require much higher memory bandwidth. System ASIC platforms enable AI applications through training in deep learning and high speed inter-node connectivity, by deploying high speed SerDes, a deep neural network DSP engine, and a high speed high bandwidth memory interface with High Bandwidth Memory (HBM) within a 2.5D system-in-package (SiP).

Open-Silicon’s implementation of a silicon-proven system ASIC platform in TSMC’s FinFET and CoWoS® technologies was initially silicon proven in 16FF+ at 2Gbps data rate, achieving bandwidths up to 256GBps. Keeping up with the ecosystem, the platform quickly evolved to support 2.4Gbps data rate, achieving bandwidths up to >300GBps in 16FFC. Open-Silicon’s next generation platform in 7FF is based on a PPA-optimized HBM2 IP subsystem supporting 3.2Gbps and beyond data rates, achieving bandwidths up to >400GBps.

This presentation will discuss the implementation challenges, solutions and methodologies available to minimize risk, optimize performance, and improve 2.5D SiP manufacturing and yield through best-in-class custom silicon solutions.

Who:
Bhupesh Dasila, Engineering Manager – Silicon Engineering group, Open-Silicon

When:
Wednesday, October 3, 1:00 – 1:30 p.m.

Where:
EDA/IP/Services Track, Santa Clara Convention Center, Santa Clara

Demonstration:

When:
Wednesday, October 3, 8:00 a.m. – 6:30 p.m.

Where:
Ecosystem Pavilion, Booth #907, Santa Clara Convention Center, Santa Clara

About Open-Silicon:
Open-Silicon, a SiFive company, is a system-optimized custom SoC solution provider. To learn more, visit  www.open-silicon.com

Featured Video
Jobs
Design Verification Engineer for Blockwork IT at Milpitas, California
CAD Engineer for Nvidia at Santa Clara, California
GPU Design Verification Engineer for AMD at Santa Clara, California
Senior Firmware Architect - Server Manageability for Nvidia at Santa Clara, California
Senior Platform Software Engineer, AI Server - GPU for Nvidia at Santa Clara, California
Sr. Silicon Design Engineer for AMD at Santa Clara, California
Upcoming Events
Phil Kaufman Award Ceremony and Banquet to be held November 6 at Hayes Mansion at Hayes Mansion 200 Edenvale Ave San Jose CA - Nov 6, 2024
SEMICON Europa 2024 at Messe München München Germany - Nov 12 - 15, 2024
DVCon Europe 2023 at Holiday Inn Munich – City Centre Munich Germany - Nov 14 - 15, 2024
SEMI MEMS & Imaging Sensors Summit, at International Conference Center Munich Germany - Nov 14, 2024



© 2024 Internet Business Systems, Inc.
670 Aberdeen Way, Milpitas, CA 95035
+1 (408) 882-6554 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy PolicyAdvertise