Highlights:

• Cadence digital, signoff and custom/analog tools achieve latest DRM and SPICE certifications for TSMC 5nm and 7nm+ process technologies
• Early customers using Cadence tools for 5nm design projects ranging from initial bring-up to full production development; customers in production with 7nm+ projects

SAN JOSE, Calif. — (BUSINESS WIRE) — October 1, 2018 — Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced its continued collaboration with TSMC to certify its design solutions for TSMC 5nm and 7nm+ FinFET process technologies for mobile and high-performance computing (HPC) designs. As part of the collaboration, the Cadence^® digital, signoff and custom/analog tools have achieved the latest Design Rule Manual (DRM) and SPICE certification for the TSMC 5nm and 7nm+ processes, and the corresponding process design kits (PDKs) are now available for download. Customers using Cadence’s implementation, signoff and custom/analog tools are already in production with 7nm+ projects, and there are multiple design projects underway with early 5nm customers.

To learn more about the Cadence full-flow digital and signoff advanced-node solutions, visit www.cadence.com/go/tsmc5and7nmdandsoip. For information about the Cadence custom/analog advanced-node solutions, visit www.cadence.com/go/tsmc5and7nmcandaoip.

5nm and 7nm+ Digital and Signoff Tool Certification

Cadence delivered a fully integrated digital implementation and signoff tool flow, which has been certified by TSMC for the latest versions of the 5nm and 7nm+ processes. For the 7nm+ process, the Cadence full-flow includes the Innovus^™ Implementation System, Quantus^™ Extraction Solution, Tempus^™ Timing Signoff Solution, Voltus^™ IC Power Integrity Solution, Voltus-Fi Custom Power Integrity Solution and Physical Verification System (PVS). For the 5nm process, the Cadence certified tools include the Innovus Implementation System, Quantus Extraction Solution, Tempus Timing Signoff Solution, Voltus IC Power Integrity Solution and Voltus-Fi Custom Power Integrity Solution.

Cadence digital and signoff tools optimized for TSMC’s 5nm and 7nm+ process provide EUV support at key layers and associated design rules that enable customers to achieve power, performance and area (PPA) savings at these advanced nodes. Some of the newest enhancements for the 5nm and 7nm+ process include via pillar-aware synthesis and feed forward guidance with the Genus^™ Synthesis Solution as well as a pin-access control routing method for cell electromigration (EM) handling and statistical EM budgeting support.

5nm and 7nm+ Custom/Analog Tool Certification

The Cadence-certified custom/analog tools for the latest versions of the TSMC 5nm and 7nm+ process technologies include the Spectre^® Accelerated Parallel Simulator (APS), Spectre eXtensive Partitioning Simulator (XPS), Spectre RF Option and Spectre Circuit Simulator, as well as the Virtuoso^® custom IC design platform, which consists of the Virtuoso Schematic Editor, Virtuoso Layout Suite, Virtuoso ADE Product Suite and Virtuoso Integrated Physical Verification System. The Layout-Dependent Effect (LDE) Electrical Analyzer is also certified for 7nm+, and the collaboration on 5nm is ongoing.

By continually enhancing design methodologies and capabilities included with the Virtuoso Advanced Node Platform for TSMC’s advanced-node processes, customers can achieve better custom physical design throughput versus traditional non-structured design methodologies via the advanced capabilities in the Virtuoso and Spectre tools.

The Virtuoso Advanced Node Platform methodology consists of features and functionality required for creating 5nm and 7nm+ designs including mixed-signal functional verification, reliability analysis and an accelerated custom placement and routing methodology, which enables customers to improve productivity and meet power, multi-patterning, density and EM requirements. Cadence also introduced new features including end-to-end constraint support, dummy insertion and advanced MIMCAP support specifically for the 5nm process.

5nm and 7nm+ Library Characterization Tool Flow

In addition to the tools certified for TSMC’s 5nm and 7nm+ process technologies, the Liberate^™ Characterization portfolio and the Liberate Variety^™ Statistical Characterization Solution have been validated to deliver accurate Liberty libraries including advanced timing, noise and power models. The solutions utilized innovative methods to characterize Liberty Variation Format (LVF) models, enabling accurate process variation signoff for low-voltage applications and to create EM models enabling signal EM optimizations and signoff.

“Our 5nm process has matured to a great degree with customers doing early design starts, while our 7nm+ technology is production ready and actively in use with mutual customers,” said Suk Lee, TSMC senior director, Design Infrastructure Marketing Division. “By collaborating closely with Cadence, we’re enabling customers to deliver innovations using our latest technologies and the Cadence certified tools and flows.”

“We’ve continued our close collaboration with TSMC on advancing 5nm and 7nm+ FinFET adoption by providing customers with access to the latest technical capabilities for advanced-node design creation,” said Dr. Chin-Chi Teng, senior vice president and general manager   of the Digital & Signoff Group at Cadence. “Based on aggressive new R&D optimizations and performance improvements to our digital and signoff and custom/analog tools, customers can deliver innovative, reliable end products in their respective markets within tight timelines.”