Dr. Andrew Walker, VP of Product at Spin Transfer Technologies, Inc (STT), will present during the Semicon West Conference. STT is developing fundamental magnetic memory technologies that position spin-transfer torque (STT)-MRAM to replace SRAM and DRAM. Dr. Walker will discuss how SRAM’s high leakage and limitations in scaling in advanced FinFET CMOS processes will soon limit the total cache capacity on the compute chip. During the New Memories program session, Dr. Walker will discuss how this “looming SRAM catastrophe” will cause bottlenecks in compute capabilities and dramatic rises in system energy use.

While there are well known concerns about the scalability issues of DRAM and NAND Flash (even with 3-D technology), SRAM is now also under scrutiny. In his presentation, Dr. Walker will discuss the advancements being made to extend MRAM from its current application as an embedded nonvolatile solution, and how it could overcome the data bottleneck and reduce system energy use. Through new innovations in the area of materials and circuit design, MRAM is starting to become an attractive replacement for SRAM. He will also discuss how this magnetic migration and subsequent innovations may allow MRAM to reach parts of the memory hierarchy that other memory types have been unable to reach.

Moscone South

Smart Manufacturing Pavilion, Meet the Experts Theatre

San Francisco, CA USA